LD2668 .T4 1966 B67 / Master of Science

Carbon nanotubes (CNTs) are known for their exceptional electrical, thermal, mechanical, optical, and chemical properties. With the significant progress in recent years on synthesis, purification and integration challenges, CNT network/array based thin-film transistors (TFTs) are likely to play a critical role as the building blocks of future electronics. CNT-TFTs can find applications in flexible, transparent and energy-efficient circuits, e-displays, solar cells, RFID tags, e-paper, touch screens, implantable medical devices and chemical/bio/optical sensors. CNTs in CNT-TFTs are deposited on low thermal conductivity substrates which can impede the heat dissipation resulting in high temperature. The excessive self-heating in CNT-TFTs can degrade the electrical and thermal performance and could potentially lead to failure of the devices. Therefore, the issues related to operational reliability of CNT-TFTs arising from the self-heating effects need to be examined and studied. In the present work, a computational approach is developed and employed to study the electrical and thermal transport in CNT-TFTs. The modeling framework can predict the current and temperature profile of CNT network/array and the supporting structure. The model is validated against the experimental results. In case of CNT network TFTs, the computational method allows us to examine the role of various device parameters such as network morphology (i.e., network density, CNT junction topology, and CNT length and alignment distribution) and channel geometry (i.e., channel length and width) on heat dissipation and thermal reliability. The simulation results help interpret experimental data and provide the quantitative information about the thermal boundary conductances at CNT junctions and CNT-substrate interfaces in CNT-TFTs. The findings suggest that the structure of CNT junctions on substrate can become very critical in CNT network TFTs as the lack of contact with the substrate at these junctions can lead to junction temperatures hundreds of degrees higher than the rest of the device, which will severely deteriorate the performance of these devices. High-field breakdown study of CNT network TFTs is also conducted which provides guidelines for the design and optimization with respect to aforementioned parameters in order to enhance the performance and reliability. Dense CNT arrays are preferred for better electrical performance in CNT array TFTs, but they also experience electrostatic and thermal cross-talk which can adversely affect the device performance. These effects have been studied in details. The role of trap charges in CNT array TFTs is also investigated to understand and mitigate hysteresis. Lastly, CNT-liquid crystal composites are studied using dissipative particle dynamics (DPD) technique with the aim to understand how the CNT concentration in composite affects the alignment of liquid crystals and to explore the method of CNT alignment using liquid crystals.

published_or_final_version / Electrical Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / abstract / Physics / Master / Master of Philosophy

No description available.

No description available.

No description available.

Pour les applications électroniques analogiques, des composants fonctionnant en hautes fréquences avec un faible niveau de bruit sont nécessaires. Pour le développement de circuits numériques hauts débits de type DCFL, il faut utiliser des transistors à effet de champ à tensions de seuil positives. De plus, la tenue en tension est aussi une contrainte. La structure HEMT métamorphique à enrichissement AlInAs/GaInAs sur GaAs développée par la société OMMIC en 2007 répond à ces exigences et constitue le point de départ de cette étude. Le but de cette thèse est en effet de fournir une structure de HEMTs à enrichissement (E-HEMTs) de la filière AlInAs/InGaAs pour applications faible bruit sur substrat InP, afin de tirer profit de sa forte mobilité électronique, tout en maintenant de bonnes caractéristiques statiques et dynamiques. Notre travail d’optimisation, de réalisation et de caractérisation de structures permet d’atteindre des fréquences de coupure FT, FMAX de respectivement 204 GHz et 327 GHz, pour un NFmin de 0.96 dB et un gain associé de 13.2 dB à 30 GHz, pour des structures présentant d’excellentes performances statiques : tension de seuil positive de 30 mV, tension de claquage grille - drain de –7 V, transconductance de 1040 mS/mm. Ces résultats placent ce HEMT sur InP à l’état de l’art des transistors HEMTs à enrichissement, et en font un concurrent des transistors HEMTs à déplétion pour les applications faible bruit. / The increasing needs of high frequency electronic systems combined with constant efforts in miniaturization require low noise and high frequency Field Effect Transistor with high operation voltage. For digital applications, enhancement mode HEMT is needed. The enhancement-mode metamorphic AlInAs/GaInAs HEMT on GaAs substrate developed in OMMIC in 2007 meet these requirements and it represents the starting point of our study. The aim of our work is to provide AlInAs/InGaAs E-HEMTs for low noise applications, on InP substrate in order to take advantage of its high electronic mobility, while maintaining high static and dynamic performances. We first optimized the structure, then we realized and characterized E-HEMTs which reach high cutoff frequencies, such as 204 GHz for FT and 327 GHz for FMAX, combined with a low noise figure of 0.96 dB and an associated gain of 13.2 dB at 30 GHz. These structures also show high static performances such as a 30 mV threshold voltage, a gate-to-drain breakdown voltage of –7 V, and a high transconductance of 1040 mS/mm. These results make this pseudomorphic E-HEMT on InP substrate at the state of the art of the enhancement mode HEMTs, and it even competes with the best low noise applications depletion mode HEMTs.

Les résonateurs électromécaniques (MEMS), de part leurs bonnes performances, leur petite taille, ou encore leurs possibilités d'intégration au plus proche des transistors, présentent un fort potentiel pour le remplacement des quartz dans les applications de référence de temps. Dans ce contexte, nous proposons de développer des résonateurs électromécaniques en vue d'une intégration « front-end », pour la réalisation d'oscillateurs intégrés. Ainsi, nous avons fabriqué des démonstrateurs à partir des briques de base de la technologie CMOS Silicon On Nothing, en phase de R&D à STMicroe!ectronlcs. Du fait de la petite taille des composants, nous avons utilisé un transistor à grille résonante pour amplifier la détection de la résonance. Ainsi, des développements technologiques spécifiques ont permis de fabriquer des résonateurs et leur transistor de détection. La conception des dispositifs a été réalisée à partir du développement d'un modèle électromécanique des résonateurs. Ce modèle est compatible avec les outils de design et peut alors aider à la conception de l'oscillateur MEMS. Nous avons ensuite montré le bon fonctionnement des résonateurs fabriqués, ainsi que celui de l'amplification induite par la détection MOS. Cette démonstration constitue une première, prouvant la fonctionnalité de la détection MOS pour un composant de petite taille, vibrant dans le plan du substrat. Enfin, nous avons validé le modèle électromécanique à partir d'autres modèles ainsi qu'avec les mesures des composants fabriqués. En termes de perspectives, le recours à diverses améliorations permettrait d'obtenir des dispositifs compatibles avec la réalisation d'un oscillateur performant et co-intégré. / Due to good performances, small size, or either integration possibilities very close to transistors,electromechanical resonators offer a strong potential for quartz replacement in time reference applications. In this context, we propose to develop electromechanical resonators in a perspective of a front-end integration, for the realization of integrated oscillators. The fabricated demonstrators are based on the Silicon On Nothing CMOS technology, under R&D at STMicroelectronics. Due to the small size of the studied components, a resonant gate transistor was used to amplify the resonance detection. Specific technological developments enabled the fabrication of both resonator and detection transistor. Device conception was made by the use of an electromechanical resonator model, developed during the study. Thurthermore, the model is compatible with design tools, making it usefull for MEMS oscillator conception.Then, we demonstrated resonator and MOSFET detection amplification well-functionning on the fabricated devices.This is the first demonstration of MOSFET detection functionality for a small size and in-plane vibrating component. Finally, the electromechanical model was validated with other models and measurements. In terms of perspectives, the use of various design or technology improvements could able the access to devices compatible with the realization of a high perfromances and co-integrated oscillator.