This thesis reports the development of two rapid thermal annealing systems, one based on resistive heating of graphite strips, the second on heating from incoherent lamp radiation. Electrical activation studies of silicon implanted gallium arsenide has been used to compare the systems with those available commercially. It has been shown that commercial systems can yield temperature measurement errors in excess of 50° C. Furthermore, the systems have been used to investigate the electrical activation of silicon implants co-implanted with other ions into gallium arsenide, with a view to either, improving the activation of the silicon for high doses, or modifying the carrier profile shape for low doses. A factor of two improvement in the electrical activation of high dose silicon implants has been achieved by the co-implantation of phosphorus, with a reduction in the annealing temperature required to achieve a given activity also being observed. An alternative processing methodology is also proposed for through- nitride implantation. Phosphorus implants have also been used to "pre-amorphise" substrates to prevent ion channelling. Providing the damage is maintained below a certain level, improvements in profile shape can be obtained. Other compensation techniques using boron and carbon implants have also been investigated. Boron has been demonstrated to provide improved carrier activation for low implant doses, with thermally stable profile modification capability as the dose is increased. The electrical activation of single carbon implants (40% maximum) is below the level of compensation of silicon implants (approximately 90%) co-implanted with carbon. This in turn means carbon is excellent for profile modification as no p-type layer is created beyond the donor implant.

L’intégration en trois dimensions se présente comme une alternative à la réduction des dimensions pour poursuivre l’augmentation continuelle de la densité des composants. Elle permet également de réduire le délai dans les interconnexions. Un autre avantage, non négligeable, est la possibilité d’ajouter de nouvelles fonctionnalités sur les niveaux supérieurs. Cependant, l’empilement de composants et leur interconnexion verticale doivent faire face à deux difficultés majeures. Tout d’abord, l’obtention d’un substrat semi-conducteur monocristallin de haute qualité sur une couche diélectrique doit s’effectuer sans détériorer les composants réalisés précédemment, en respectant une température limite. Ensuite, les composants supérieurs doivent être alignés avec précision par rapport au niveau inférieur, et doivent être intégrés tout en respectant le budget thermique imposé par les transistors déjà existants.Dans ce contexte, cette thèse s’attache à démontrer une approche innovante pour la synthèse de la couche active supérieure, en utilisant la croissance par CVD catalytique (VLS) confinée et guidée à l’intérieur d’une cavité. Ce manuscrit est composé de 4 chapitres : Le premier chapitre rappelle les notions de base des dispositifs et technologies MOS et fournit une analyse des différentes sources de dégradation liées à la miniaturisation. L’intégration en trois dimensions est ensuite introduite, accompagnée des différents procédés de fabrication. Une autre méthode de synthèse de silicium monocristallin plus originale est proposée : la croissance VLS. Le deuxième chapitre est consacré à la croissance VLS de nanofils de silicium sur substrat amorphe. L’aspect théorique et l’optimisation de la recette de croissance sont détaillés. Ainsi, des nanofils de silicium rectilignes avec des diamètres et des positions parfaitement contrôlés sont obtenus grâce à des motifs catalytiques définis par lift-off. Dans le troisième chapitre, une méthode de fabrication de cavité compatible avec l’approche 3D est proposée afin de contrôler avec précision les dimensions et la position du silicium formée par VLS. Une étude de la croissance de nanolames par VLS confinée dans ces cavités est proposée. Deux techniques de caractérisation structurale complémentaires (EBSD, STEM) sont utilisées afin d’analyser en détail la structure du silicium. Le dernier chapitre présente la fabrication de transistors MOS en utilisant les lames de silicium produites par VLS comme canal de conduction. L’intégration de transistors à grille arrière nous a permis de déterminer les paramètres élémentaires du transport et de les comparer à ceux des substrats SOI commerciaux. / Three-dimensional integration of semiconductor devices is perceived as an alternative to device scaling in order to continue the increasing of the devices density. Moreover, it can reduce interconnect delay. Finally it allows the addition of different technologies in the back-end of the line, therefore enabling more applications. 3D integration requires the stacking of active layers alternated with interlayer dielectrics (ILD). The first challenge consists in growing crystal quality semiconductor starting on an amorphous substrate. The second difficulty concerns the device integration: the alignment registration between several active layers must be accurate and the temperature of fabrication is limited by the silicidation thermal budget of transistors integrated in inferior layers. In this context, this thesis demonstrates the synthesis of the crystalline silicon active layers using a new method, namely, the catalytic confined and guided Vapor-Liquid-Solid (VLS) growth.This manuscript is organized into four chapters: The first chapter develops fundamental notions associated to MOS devices and technologies, and provides an analysis of parasitic effects due to miniaturization. Three-dimensional integration is subsequently introduced with a detailed discussion on fabrication process. A new method is proposed to grow crystal semiconductor on an amorphous layer: the VLS growth. The second chapter is devoted to the VLS growth of silicon nanowires on an amorphous substrate. The theoretical aspect and the recipe optimization are developed. The localization of nanowires is controlled by catalyst patterns made by lift-off. In the third chapter, one method of cavity fabrication is proposed in order to control with accuracy dimensions and position of silicon blade synthetized by VLS. The single crystalline nature of silicon has been checked based on complementary techniques: Electron Back-Scattered Diffraction (EBSD) and Scanning Transmission Electron Microscopy (STEM). The last chapter presents the electrical characterization of VLS grown silicon nanoribbons. For that sake, “pseudo-MOS” transistors have been fabricated using VLS grown silicon blade as conduction channel and back-gate control. The characteristics of these transistors were extracted and compared to that of commercial SOI thin films.

The incorporation of Si1-xGex alloy heterostructures into conventional Si processes has been proposed as a means of improving the operating frequency and overall performance of Si field effect transistors. One parameter expected to benefit from this approach is the hole mobility, which would have important implications for high speed CMOS applications. Measured values of the hole mobility, however, have failed to live up to early expectations, and much ongoing research is directed at understanding whether this is an intrinsic limitation (e.g. due to alloy disorder scattering), or due to imperfections arising in the growth and fabrication process. In this thesis, a detailed theoretical study is presented of the hole mobility in single sub-band Si1-xGex heterostructures.

No description available.

Le contexte de ce travail de thèse s’inscrit dans les récents progrès des performances en gamme millimétrique des composants silicium tels que les MOSFET et les HBT SiGe. La situation actuelle en termes de circuits à base de silicium est limitée en fréquence autour de 60 GHz, seuls quelques résultats au-delà de 100 GHz ont d’ores et déjà été publiés. Dans ce contexte, il est maintenant nécessaire de savoir si les nouvelles et futures générations de transistors silicium peuvent adresser des fréquences encore plus élevées (jusque 220 GHz). Ces applications pourraient être des blocs d’émission réception à faible portée et très haut débit. Les aspects inconnus sont : 1) la validité des techniques de mesures sur silicium jusque 220 GHz ; 2) le comportement fréquentiel des transistors silicium jusque 220 GHz ; 3) la modélisation des transistors dans ces gammes de fréquences nécessaire à la conception de fonctions millimétriques. Des études à partir de simulations électromagnétiques ont été menées afin d’optimiser les structures de test (accès et topologie optimale des transistors). Ce travail est accentué sur les techniques de calibrage et d’épluchage sous pointes jusque 220 GHz. De plus, les études ont été orientées, d’une part, sur l’amélioration des modèles électriques des transistors jusque 220 GHz et d’autre part, la validité des modèles de bruit jusqu’en bande W (75-110 GHz). Pour cet aspect, le travail a été orienté sur l’élaboration de deux méthodes de mesure permettant de valider les modèles de bruit par des méthodes de mesures transférables en milieu industriel. A partir de ces modèles établis et validés, des démonstrateurs ont été réalisés fonctionnant en bande G. / The motivation of this work inherits from the recent progress in terms of cut-off frequencies of silicon transistors such as MOSFET (bulk and SOI) and SiGe HBT. In 2006, the state-of-the-art cut-off frequencies achieved more than 300 GHz. Nowadays, silicon circuits are limited around 60 GHz, only few with the exception of few circuits which operate at frequencies higher than 100 GHz (VCO at 130 GHz with SiGe HBT). In this context, it is highly required to check the ability of new and future generations of silicon transistors to provide higher cut-off frequencies especially in G band (140-220 GHz). These applications could be transmitter-receiver systems with high data rates and short distances. The unknown aspects are: 1) the validation of silicon transistors measurement up to 220 GHz; 2) the frequency behaviour of silicon transistors up to 220 GHz; 3) the modelling of these transistors. Electromagnetic simulations have been employed to optimize the test structures (the layout of the transistor). This work is particularly interested in calibration and de-embedding techniques for on-wafer measurements up to 220 GHz. Studies have been carried out on the small signal equivalent circuit improvement as well as the validation of the noise models in W band (75-110 GHz). From these validated models, pre-adapted transistors have been realised in G band. The development of measurement techniques adequate for the industry is the purpose of this work.

The increasing demand for high performance as well as low standby power devices has been the main reason for the aggressive scaling of conventional CMOS transistors. Current devices are at the 32nm technology node. However, due to physical limitations as well as increase in short-channel effects, leakage, power dissipation, this scaling trend cannot continue and will eventually hit a barrier. In order to overcome this, alternate device topologies have to be considered altogether. Extensive research on ultra thin body double gate FETs and gate all around nanowire FETs has shown a lot of promise. Under strong inversion, these devices have demonstrated increased performance over their bulk counterparts. This is mainly attributed to full carrier inversion in the body. However, these devices are still limited by lithographic and processing challenges making them unsuitable for commercial production. This thesis explores a unique device structure called the CFET (Cylindrical Field Effect Transistors) which also like the above, relies on complete inversion of carriers in the body/bulk. Using dual gates; an outer and an inner gate, full-volume inversion is possible with benefits such as enhanced drive currents, high Ion/Ioff ratios and reduced short channel effects.

A detailed study of a MOS-Bipolar power semiconductor known as the IGT or COMFET or GEMFET was undertaken. The major disadvantage of the device was identified as latching and the effect of various factors affecting latching were determined. The experiments performed determined susceptibility to latch under various conditions of temperature, rate of rise of gate-source voltage and rate of fall of drain-source voltage. A 340V, lOA three phase GEMFET bridge inverter using a pulse width modulation scheme to drive a permanent magnet brushless dc motor was successfully fabricated. The simplicity of the gate drive circuit and the low cost of the device make the IGT ideal for motor drive applications. / M.S.

No description available.

The objective of this work is to understand how the thin film characteristics of p-type organic and polymer semiconductors affect their electronic properties in microelectronic applications. To achieve this goal, three main objectives were drawn out: (1) to create single-crystal organic field-effect transistors and measure the intrinsic charge carrier mobility, (2) to develop a platform for measuring and depositing polymer thin films for organic field-effect transistors, and (3) to deposit polythiophene thin films for inorganic-organic hybrid solar cells and determine how thin film properties effect device performance. Pentacene single-crystal field-effect transistors (OFETs) were successfully manufactured on crystals grown via horizontal vapor-phase reactors designed for simultaneous ultrapurification and crystal growth. These OFETs led to calculated pentacene field-effect mobility of 2.2 cm2/Vs. During the sublimation of pentacene at atmospheric pressure, a pentacene disporportionation reaction was observed whereby pentacene reacted with itself to form a peripentacene, a 2:1 cocrystal of pentacene:6,13-dihydropentacene and 6,13-dihydropentacene. This has led to the proposal of a possible mechanism for the observed disproportionation reaction similar to other polyaromatic hydrocarbons, which may be a precursor for explaining the formation of graphite. Several silicon-based and PET-based field-effect transistor platforms were developed for the measurement of mobility of materials in the thin film state. These platforms were critically examined against one another and the single-crystal devices in order to determine the optimal device design for highest possible mobility data, both theoretically based on silicon technology and commercially based on individual devices on flexible substrates. Novel FET device designs were constructed with a single gate per device on silicon and PET as well as the commonly used common-gate device. It was found that the deplanarization effects and poor gate insulator quality of the individual gate devices led to lower overall performance when compared to the common gate approach; however, good transistor behavior was observed with field modulation. Additionally, these thin films were implemented into inorganic-organic hybrid and purely organic solid-state photovoltaic cells. A correlation was drawn between the thin film properties of the device materials and the overall performance of the device. It was determined that each subsequent layer deposited on the device led to a planarization effect, and that the more pristine the individual layer, the better device performance. The hybrid cells performed at VOC = 0.8V and JSC = 55A/cm2.

Il a été démontré que la structure gate-all-around en nanofils de silicium peut radicalement supprimer les effets de canaux courts. De plus, l'introduction d'espaceurs internes entre ces nanofils peut permettre de contrôler la tension de seuil, à l'aide d'une deuxième grille de contrôle. Ces technologies permettent d'obtenir une consommation électrique extrêmement faible. Dans cette thèse, pour obtenir des opérations à haute vitesse (pour augmenter le courant de drain), la technique de réduction de la résistance source/drain sera débattue. Les propriétés de transport électronique des NWs empilées verticalement seront analysées en détail. De plus, des simulations numériques sont effectuées pour examiner les facultés de contrôle de leur tension de seuil utilisant des grilles sépares. / This thesis is titled “A Study on Carrier Transport Properties of Vertically-Stacked Nanowire Transistors,” and is organized in seven chapters in English. 　 Gate-all-around (GAA) silicon nanowire transistors (SNWTs) are one of the best structures to suppress short channel effect for future CMOS devices. In addition, vertically-stacked channel structure benefits from high on-state current owing to reduced footprint. In this thesis, the carrier transport properties of vertically-stacked GAA SNWTs have been experimentally investigated. The vertically-stacked GAA SNWTs were fabricated on SOI wafers by selective etching of SiGe layers in epitaxially-grown Si/SiGe superlattice and top-down CMOS process. The experimental results reveal stacked-channel structure can achieve superior on-state current. It was also found that the effective mobility decreases with diminishing nanowire cross-section width from 30 nm down to 5 nm. This study gives basis and guidelines to optimize the performance of GAA SNWTs for future CMOS devices.