Il a été démontré que la structure gate-all-around en nanofils de silicium peut radicalement supprimer les effets de canaux courts. De plus, l'introduction d'espaceurs internes entre ces nanofils peut permettre de contrôler la tension de seuil, à l'aide d'une deuxième grille de contrôle. Ces technologies permettent d'obtenir une consommation électrique extrêmement faible. Dans cette thèse, pour obtenir des opérations à haute vitesse (pour augmenter le courant de drain), la technique de réduction de la résistance source/drain sera débattue. Les propriétés de transport électronique des NWs empilées verticalement seront analysées en détail. De plus, des simulations numériques sont effectuées pour examiner les facultés de contrôle de leur tension de seuil utilisant des grilles sépares. / This thesis is titled “A Study on Carrier Transport Properties of Vertically-Stacked Nanowire Transistors,” and is organized in seven chapters in English. 　 Gate-all-around (GAA) silicon nanowire transistors (SNWTs) are one of the best structures to suppress short channel effect for future CMOS devices. In addition, vertically-stacked channel structure benefits from high on-state current owing to reduced footprint. In this thesis, the carrier transport properties of vertically-stacked GAA SNWTs have been experimentally investigated. The vertically-stacked GAA SNWTs were fabricated on SOI wafers by selective etching of SiGe layers in epitaxially-grown Si/SiGe superlattice and top-down CMOS process. The experimental results reveal stacked-channel structure can achieve superior on-state current. It was also found that the effective mobility decreases with diminishing nanowire cross-section width from 30 nm down to 5 nm. This study gives basis and guidelines to optimize the performance of GAA SNWTs for future CMOS devices.

<p>The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.</p>

The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.