This work investigates advanced single-electron transistor (SET) devices for detection of charge motion in solid-state systems. In particular, novel, nanoscale twin-SET and double-island SET (DISET) detectors are introduced as sensitive charge detectors. Some advantages over conventional SET detectors in terms of noise performance, sensitivity and versatility are pointed out. With the prospect of present, transistor-based microelectronics facing serious limitations due to quantum effects and heat dissipation, alternative computing paradigms ??? such as quantum computers, quantum-dot cellular automata and single-electronics ??? have emerged, promising an extension of highlevel integration and computing power beyond the above limitations. The most promising proposals are based on solid-state systems, and readout of a computational result often requires ultra-sensitive charge detectors capable of sensing the motion of single charges on fast timescales. SETs have been shown to combine all these qualities. However, random fluctuations of the background charge in solid-state systems can affect SETs and cause errors during readout. A twin-SET detector is presented that consists of two independent SETs, which were used to detect controlled single electron transfers on a small, floating metal double-dot. By cross-correlating the two SET signals, rejection of random charge noise is successfully demonstrated, thus decreasing the error probability during readout. Detection of single-electron transfer in a double-dot is also demonstrated using a double-island SET. In addition, conductance suppression in this novel DISET detector allows the detection of electrostatically degenerate charge con- figurations of a double-dot, which cannot be achieved with single-island SETs. We consider the noise performance of the DISET, and an intuitive definition of the DISET charge sensitivity suggests that under certain conditions, DISETs can have a better charge sensitivity than conventional SETs, which would be attractive for quantum limited measurements. Finally we present the first study of a DISET operated at radio-frequencies (rf-DISET), compatible with charge detection on ms timescales. This capability is a prerequisite when reading out the charge state of quantum mechanical systems. A very good charge sensitivity (5.6 x 10i6 e/pHz) and noise temperature (2.1 K) of the rf-DISET setup are reported.

As Si MOS approaches its maximum limits in speed and bandwidth, new devices are desired to meet the needs of high speed communications and signal processing. A device that exhibits superior performance to Si MOS, BJT, and GaAs technology is the HEMT (high electron mobility transistor). The HEMT offers superior transconductance, mobility, speed, and noise performance compared to Si MOS, BJT, and standard GaAs technology. The high performance is a result of improved channel mobility due to a heterojunction. At the heterointerface, the majority carriers are confined to a very thin sheet forming what has been termed a 2DEG (two dimensional electron gas). The purpose of this thesis is to demonstrate the suitability of Honeywell's delta-doped self-aligned complimentary HIGFET process for the realization of high speed analog circuits. An operational amplifier and switched-capacitor circuit are presented. The operational amplifier has been fabricated at Honeywell and preliminary tests have been performed on the op-amp which are also presented. / Graduation date: 1998

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2006. / Includes bibliographical references. Also available in electronic version.

Split and normal gate A1GaAs /GaAs MODFETs were fabricated along with the ohmic test structures and the Hall bar geometries. The DC characteristics of normal gate transistors were evaluated at room temperature and at 77K and the threshold voltages were extracted from the measurements and compared to the theoretical results. The performance of normal gate transistors was reasonable. The sheet carrier density and the mobility extracted from Hall measurements using the Hall bar geometry showed increase of carrier density with increasing gate voltage and an increase of mobility with increasing carrier density. The contact resistance obtained from the ohmic test structure was high and not uniform within the sample. / Graduation date: 1991

Thèse doctorat : Dispositifs de l'Electronique Intégrée : Villeurbanne, INSA : 2005. / Contient 1 glossaire. Titre provenant de l'écran-titre. Bibliogr. p. 210-223.

Thesis (Ph.D.)--University of Central Florida, 2009. / Adviser: Michael N. Leuenberger. Includes bibliographical references (p. 104-115).

In general, La-based high-k gate dielectric owns superior properties to offer transistor excellent characteristics. Thus, amorphous InGaZnO thin-film transistor with La-based high-k gate dielectric has been investigated in this thesis. Different approaches have been adopted to improve the device performance. First of all, the influence of gate-dielectric annealing in oxygen for different times on the device characteristics of the amorphous InGaZnO thin-film transistor with HfLaO gate dielectric has been investigated. It is demonstrated that this annealing treatment can effectively suppress the negative oxide charges. Moreover, it is discovered that this annealing treatment can suppress the acceptor-like border and interface traps. Accordingly, a high saturation carrier mobility of 35.2 〖cm〗^2/V∙s is achieved for the 30’-annealed device. Then, the effects of dielectric-annealing gas (O2, N2 and NH3) for a fixed annealing time of 10 min on the device characteristics are studied, and improvements by the dielectric annealing are observed for each gas. Among the samples, the N2-annealed sample has a high saturation carrier mobility of 35.1 〖cm〗^2/V∙s, the lowest subthreshold swing of 0.206 V/dec and a negligible hysteresis. On the contrary, the O2-annealed sample shows poorer performance due to a decrease of electron concentration in InGaZnO. Furthermore, the NH3-annealed sample displays the lowest threshold voltage (1.95 V) due to increased gate-oxide capacitance and generated positive oxide charges. Next, the effects of fluorine incorporation in amorphous InGaZnO by ion implant on the characteristics of InGaZnO thin-film transistor have been investigated. The electrical characteristics can be improved by this treatment due to increase of carrier concentration and passivation of defects in the InGaZnO film. Consequently, the saturation carrier mobility can be increased to 34.0 〖cm〗^2/V∙s, and the output current can be nearly doubled. However, device degradation is observed for very high fluorine dose above 1.0×1015 /〖cm〗^2. Then, another method for fluorine incorporation has been studied by treating the amorphous InGaZnO film in a CHF3/O2 plasma. The saturation carrier mobility can be improved to as high as 39.8 〖cm〗^2/V∙s. Then, a new high-k material is proposed by investigating the effects of Ta incorporation in the La2O3 gate dielectric of amorphous InGaZnO thin-film transistor. Since the Ta incorporation is found to effectively enhance the moisture resistance of the La2O3 film, both the dielectric roughness and trap density at/near the InGaZnO/dielectric interface can be reduced, resulting in a significant improvement in the electrical characteristics of the device. Nevertheless, excessive incorporation of Ta can degrade the device characteristics due to newly-generated Ta-related traps. Finally, the proposed TaLaO is compared with Ta2O5 as the gate dielectric of amorphous InGaZnO thin-film transistor. It is found that the electrical characteristics of the device can be effectively improved by the incorporation of La in the Ta2O5 gate dielectric, which is ascribed to the fact that La incorporation can enlarge the band gap of Ta oxide and its conduction-band offset with InGaZnO, and also reduce the trap densities in the Ta2O5 gate dielectric and at the InGaZnO/gate-dielectric interface. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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This thesis deals with some of the theoretical and practical aspects relating to the conversion gain and noise performance of mixers employing dual-gate field effect transistors (DGFET'S) . To start with, the role of mixers in the context of radio conununication receivers is highlighted and the most relevant mixer properties are explained. Solid state mixing devices and their circuits are then discussed with special emphasis on the DGFET.This includes a survey and explanation of mixing devices ,planar transmission lines and circuit components for the practical design of mixers. Chapter 3 then deals with the mixer signal analysis as well as accuracy considerations. A more detailed treatment of the DGFET in terms of structure and dc model is given in the subsequent chapter. Problems associated with the choice of an FET model are referred to as well as the use of MATLAB for computationa: purposes. This is followed in the next two chapters with the development and analysis of the large signal equivalent circuit of tr.{· DGFET,and a treatment of noise and its measurement as associated with mixers. The design, practical implementation and measurement of the properties of DGFET mixers is covered in chapter 7. This is followed in Chapter 8 by an overall discussion of results, possible future work and conclusions. A new FET model is proposed that enables the dc characteristics to be simulated more closely than in previous models, particularly at low drain voltages. Furthermore, the representation of the noise by a frequency independent drain current generator and an input noise conductance enabled a single set of measurements to simulate the noise behaviour of the device as an amplifier or a mixer. Practical investigations using an NEe device type NE 41137 gave a maximum stable conversion gain in the frequency range O.SGHz to 3.0GHz of 4dB with a minimum noise figure 8.SdB.