One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding that does not use the coprocessor. / En teknik som används för att minska de fel som en signal utsätts för vid transmission över en brusig kanal är felrättande kodning. Ett exempel på sådan kodning som ger ett mycket bra resultat är turbokodning. I några digitalsignalprocessorer, av sorten TMS320C64xTM, finns en inbyggd coprocessor som utför turboavkodning. Denna uppsats är utförd åt Communication Development inom Saab AB och presenterar en utvärdering av denna coprocessor. Utvärderingen avser såväl minnesförbrukning som datatakt och innehåller även en jämförelse med en implementering av turbokodning utan att använda coprocessorn.

Este trabalho investiga a decodificação turbo de códigos produto construídos a partir de códigos de Reed-Solomon sobre constelações QAM. Por meio da geometria euclidiana da constelação utilizada e das relações dos elementos de campo de Galois utilizados na codificação Reed-Solomon com os símbolos pertencentes ao alfabeto de modulação, é proposto um algoritmo de decodificação que utiliza a localização geométrica dos símbolos recebidos no processo de decodificação turbo. Tanto a primeira etapa da decodificação SISO baseada no algoritmo de Chase, como a extração da informação extrínseca baseada no algoritmo proposto por Pyndiah, são tratadas pelo uso de uma abordagem geométrica sobre o espaço euclidiano. Os resultados de simulação utilizando o algoritmo proposto coincidem com aqueles usando a decomposição e análise pragmática binária, sendo que a abordagem apresentada conduz a simplificações e otimizações em relação à metodologia binária no que ser refere à implementação dos possíveis esquemas de decodificação. / This work investigates the turbo decoding of product codes built using Reed- Solomon codes in QAM constellations. Using the euclidian geometry of the constellation and the relations of the Galois field elements used in the Reed-Solomon code and the modulation alphabet, a decoding algorithm for the turbo decoding process is proposed using the geometric localization of the received symbol. Both the first stage of the SISO decoding based on the Chase algorithm, as the calculation of the extrinsic information based on the Pyndiah algorithm, are treated using the geometric approach in the euclidian space. The simulations show that this algorithm gives similar performance results as the pragmatic binary decomposition approach, and leads to simplifications and optimizations in decoding implementations schemes compared to the former.

Este trabalho investiga a decodificação turbo de códigos produto construídos a partir de códigos de Reed-Solomon sobre constelações QAM. Por meio da geometria euclidiana da constelação utilizada e das relações dos elementos de campo de Galois utilizados na codificação Reed-Solomon com os símbolos pertencentes ao alfabeto de modulação, é proposto um algoritmo de decodificação que utiliza a localização geométrica dos símbolos recebidos no processo de decodificação turbo. Tanto a primeira etapa da decodificação SISO baseada no algoritmo de Chase, como a extração da informação extrínseca baseada no algoritmo proposto por Pyndiah, são tratadas pelo uso de uma abordagem geométrica sobre o espaço euclidiano. Os resultados de simulação utilizando o algoritmo proposto coincidem com aqueles usando a decomposição e análise pragmática binária, sendo que a abordagem apresentada conduz a simplificações e otimizações em relação à metodologia binária no que ser refere à implementação dos possíveis esquemas de decodificação. / This work investigates the turbo decoding of product codes built using Reed- Solomon codes in QAM constellations. Using the euclidian geometry of the constellation and the relations of the Galois field elements used in the Reed-Solomon code and the modulation alphabet, a decoding algorithm for the turbo decoding process is proposed using the geometric localization of the received symbol. Both the first stage of the SISO decoding based on the Chase algorithm, as the calculation of the extrinsic information based on the Pyndiah algorithm, are treated using the geometric approach in the euclidian space. The simulations show that this algorithm gives similar performance results as the pragmatic binary decomposition approach, and leads to simplifications and optimizations in decoding implementations schemes compared to the former.

du fait de l'explosion actuelle des télécommunications, les opérateurs sont victimes d'une crise de croissance les obligeant à installer toujours plus de relais, à découper les cellules (zone de couverture d'un relais) en micro-cellules dans les grandes villes, afin de faire face à la demande toujours grandissante de communications. Les concepteurs des nouveaux réseaux de transmission sont donc constamment à la recherche d'une utilisation plus efficace des ressources disponibles

The main objective of this thesis is to propose new methods for designing high-performance embedded computer system architectures. To achieve the goal, three major components - multi-core processing elements (PEs), DRAM main memory systems, and on/off-chip interconnection networks - in multi-processor embedded systems are examined in each section respectively. The first section of this thesis presents architectural enhancements to graphics processing units (GPUs), one of the multi- or many-core PEs, for improving performance of embedded applications. An embedded application is first mapped onto GPUs to explore the design space, and then architectural enhancements to existing GPUs are proposed for improving throughput of the embedded application. The second section proposes high-performance buffer mapping methods, which exploit useful features of DRAM main memory systems, in DSP multi-processor systems. The memory wall problem becomes increasingly severe in multiprocessor environments because of communication and synchronization overheads. To alleviate the memory wall problem, this section exploits bank concurrency and page mode access of DRAM main memory systems for increasing the performance of multiprocessor DSP systems. The final section presents a network-centric Turbo decoder and network-centric FFT processors. In the era of multi-processor systems, an interconnection network is another performance bottleneck. To handle heavy communication traffic, this section applies a crossbar switch - one of the indirect networks - to the parallel Turbo decoder, and applies a mesh topology to the parallel FFT processors. When designing the mesh FFT processors, a very different approach is taken to improve performance; an optical fiber is used as a new interconnection medium.

<p>Turbo codes was first presented in 1993 by C. Berrou, A. Glavieux and P. Thitimajshima. Since then this class of error correcting codes has become one of the most popular, because of its good properties. The turbo codes are able to come very close to theoretical limit, the Shannon limit. Turbo codes are for example used in the third generation of mobile phone (3G) and in the standard IEEE 802.16 (WiMAX).</p><p>There are some drawbacks with the algorithm for decoding turbo codes. The deocoder uses a Maximum A Posteriori (MAP) algorithm, which is a complex algorith. Because of the use of many variables in the decoder the decoding circuit will consume a lot of power due to memory accesses and internal communication. One way in which this can be reduced is to make early decisions.</p><p>In this work I have focused on making early decision of the encoder states. One major part of the work was also to be sure that the expressions were written in a way that as few variables as possible are needed. A termination condition is also introduced. Simulations based on estimations of the number of memory accesses, shows that the number of memory accesses will significantly decrease.</p>

Turbo codes was first presented in 1993 by C. Berrou, A. Glavieux and P. Thitimajshima. Since then this class of error correcting codes has become one of the most popular, because of its good properties. The turbo codes are able to come very close to theoretical limit, the Shannon limit. Turbo codes are for example used in the third generation of mobile phone (3G) and in the standard IEEE 802.16 (WiMAX). There are some drawbacks with the algorithm for decoding turbo codes. The deocoder uses a Maximum A Posteriori (MAP) algorithm, which is a complex algorith. Because of the use of many variables in the decoder the decoding circuit will consume a lot of power due to memory accesses and internal communication. One way in which this can be reduced is to make early decisions. In this work I have focused on making early decision of the encoder states. One major part of the work was also to be sure that the expressions were written in a way that as few variables as possible are needed. A termination condition is also introduced. Simulations based on estimations of the number of memory accesses, shows that the number of memory accesses will significantly decrease.

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. This dissertation presents the decoder architectures for regular and irregular LDPC codes that provide substantial gains over existing academic and commercial implementations. Several structured properties of LDPC codes and decoding algorithms are observed and are used to construct hardware implementation with reduced processing complexity. The proposed architectures utilize an on-the-fly computation paradigm which permits scheduling of the computations in a way that the memory requirements and re-computations are reduced. Using this paradigm, the run-time configurable and multi-rate VLSI architectures for the rate compatible array LDPC codes and irregular block LDPC codes are designed. Rate compatible array codes are considered for DSL applications. Irregular block LDPC codes are proposed for IEEE 802.16e, IEEE 802.11n, and IEEE 802.20. When compared with a recent implementation of an 802.11n LDPC decoder, the proposed decoder reduces the logic complexity by 6.45x and memory complexity by 2x for a given data throughput. When compared to the latest reported multi-rate decoders, this decoder design has an area efficiency of around 5.5x and energy efficiency of 2.6x for a given data throughput. The numbers are normalized for a 180nm CMOS process. Properly designed array codes have low error floors and meet the requirements of magnetic channel and other applications which need several Gbps of data throughput. A high throughput and fixed code architecture for array LDPC codes has been designed. No modification to the code is performed as this can result in high error floors. This parallel decoder architecture has no routing congestion and is scalable for longer block lengths. When compared to the latest fixed code parallel decoders in the literature, this design has an area efficiency of around 36x and an energy efficiency of 3x for a given data throughput. Again, the numbers are normalized for a 180nm CMOS process. In summary, the design and analysis details of the proposed architectures are described in this dissertation. The results from the extensive simulation and VHDL verification on FPGA and ASIC design platforms are also presented.

Tato disertační práce se zabývá analýzou, simulací a měřením zpracování a přenosu signálů digitální televize pro příjem mobilního TV vysílání ve standardech DVB-H a DVB-SH. Tyto standardy vycházejí z předpokladu, že příjem signálu je charakterizován modely přenosových kanálů s vícecestným šířením. Tyto, tzv. únikové kanály, jsou charakterizovány hlavně zpožděním a ziskem jednotlivých cest. V závislosti na dalších parametrech (rychlost přijímače, Dopplerovské spektrum), je možné rozdělit únikové kanály do třech hlavních skupin: mobilní, přenosné a fixní. Dá se předpokládat, že v různých modelech kanálů bude přenášený signál různě ovlivněn. Proto je potřebné najít optimální parametry systémů (DVB-H/SH) pro kvalitní příjem vysílaných služeb mobilní televize, což je hlavním cílem této disertační práci. Pro tento účel byly vytvořeny dvě vhodné aplikace (jedna pro DVB-H a jedna pro DVB-SH) s GUI v prostředí MATLAB, které umožňují simulovat a analyzovat míru zkreslení signálu v případě mobilních, přenosných a fixních scénářů přenosu. Navíc, tyto aplikace obsahují i druhý samostatný simulátor pro nastavení a modifikaci parametrů jednotlivých přenosových cest. Díky tomu je možné zhodnotit vliv parametrů celého systému a kanálových modelů na dosaženou chybovost (BER a MER) a kvalitu přenosu. Ve všech přenosových scénářích (v závislosti na poměru C/N) byly získané, vyhodnocené a diskutované zkreslení signálů. Navíc, u standardu DVB-H, všechny získané výsledky ze simulací byly ověřeny měřením. Rozdíly mezi dosaženými výsledky (simulace a měření) byly rovněž podrobeny diskuzi. Tuto disertační práci je možné rozdělit do čtyř hlavních částí. První část disertační práce se zabývá rešerší současného vývoje v oblasti digitálního televizního vysílání na mobilní terminály ve standardech DVB-H/SH. Na konci této části jsou jasně popsány cíle této disertační práce. Druhá část práce je zaměřená na stručný popis blokového diagramu vysílačů v obou standardech DVB-H/SH. Dále jsou stručně popsány modely přenosových kanálů, které se používají pro modelování přenosu signálu. Stručný popis vytvořených aplikací, i s vývojovým diagramem, které jsou vhodné pro simulaci a analýzu přenosu v DVB-H/SH, jsou popsány v třetí části práce. Čtvrtá a nejdelší část této disertační práce se zabývá vyhodnocením získaných výsledků ze simulací a měření.