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Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn and Balasubramaniam Natarajan / This thesis presents an energy harvesting wireless sensor network (EHWSN) architecture customized for use within a space suit. The contribution of this research spans both physical (PHY) layer energy harvesting transceiver design and appropriate medium access control (MAC) layer solutions. The EHWSN architecture consists of a star topology with two types of transceiver nodes: a powered Gateway Radio (GR) node and multiple energy harvesting (EH) Bio-Sensor Radio (BSR) nodes. A GR node works as a central controller to receive data from BSR nodes and manages the EHWSN via command packets; low power BSR nodes work to obtain biological signals, packetize the data and transmit it to the GR node. To demonstrate the feasibility of an EHWSN at the PHY layer, a representative BSR node is designed and implemented. The BSR node is powered by a thermal energy harvesting system (TEHS) which exploits the difference between the temperatures of a space suit's cooling garment and the astronaut's body. It is shown that through appropriate control of the duty-cycle in transmission and receiving modes, it is possible for the transceiver to operate with less than 1mW power generated by the TEHS. A super capacitor, energy storage of TEHS, acts as an energy buffer between TEHS and power consuming units (processing units and transceiver radio). The super capacitor charges when a BSR node is in sleep mode and discharges when the node is active. The node switches from sleep mode to active mode whenever the super capacitor is fully charged. A voltage level monitor detects the system's energy level by measuring voltage across the super capacitor. Since the power generated by the TEHS is extremely low(less than 1mW) and a BSR node consumes relatively high power (approximately 250mW) during active mode, a BSR node must work under an extremely low duty cycle (approximately 0.4%). This ultra-low duty cycle complicates MAC layer design because a BSR node must sleep for more than 99.6% of overall operation time. Another challenge for MAC layer design is the inability to predict when the BSR node awakens from sleep mode due to unpredictability of the harvested energy. Therefore, two feasible MAC layer designs, CSA (carrier sense ALOHA based)-MAC and GRI (gateway radio initialized)-MAC, are proposed in this thesis.

Today, medical implants such as cardiac pacemakers, neurostimulators, hearing aids anddrug delivery systems are increasinglymore important and frequently used in the health caresystem. This type of devices have historically used inductive coupling as communicationmedium. Newdemands on accessibility and increased performance in technology drives newresearch toward using radio communications. The FCCMICS radio standard are specificallydevoted for implantable devices.Basically all published research on transmitters in this area are using frequency shift keying(FSK) modulation. The purpose of this thesis is to explore the viability of using phase shiftkeying (PSK) modulation in ultra low power transmitters and suggest suitable architectures.

Ultra-low-power circuits are becoming more desirable due to growing portable device markets and they are also becoming more interesting and applicable today in biomedical, pharmacy and sensor networking applications because of the nano-metric scaling and CMOS reliability improvements. In this thesis, three main achievements are presented in ultra-low-power adders. First, a new majority function algorithm for carry and the sum generation is presented. Then with this algorithm and implied new architecture, we achieved a circuit with 75mV supply voltage operation. Last but not least, a 64 bit current-mode majority-function adder based on the new architecture and algorithm is successfully tested at 75mV supply voltage. The circuit consumed 4.5nW or 3.8pJ in one of the worst conditions.

Ultra-low-power circuits are becoming more desirable due to growing portable device markets and they are also becoming more interesting and applicable today in biomedical, pharmacy and sensor networking applications because of the nano-metric scaling and CMOS reliability improvements. In this thesis, three main achievements are presented in ultra-low-power adders. First, a new majority function algorithm for carry and the sum generation is presented. Then with this algorithm and implied new architecture, we achieved a circuit with 75mV supply voltage operation. Last but not least, a 64 bit current-mode majority-function adder based on the new architecture and algorithm is successfully tested at 75mV supply voltage. The circuit consumed 4.5nW or 3.8pJ in one of the worst conditions.

Nowadays, integrated circuits (IC) are mostly implemented using Complementary Metal Oxide Semiconductor (CMOS) transistor technology. This technology has allowed the chip industry to shrink transistors and thus increase the device density, circuit complexity, operation speed, and computation power of the ICs. However, in recent years, the scaling of transistor has faced multiple roadblocks, which will eventually lead the scaling to an end as it approaches physical and economic limits. The dominance of sub-threshold leakage, which slows down the scaling of threshold voltage VTH and the supply voltage VDD, has resulted in high power density on chips. Furthermore, even widely popular solutions such as parallel and multi-core computing have not been able to fully address that problem. These drawbacks have overshadowed the benefits of transistor scaling. With the dawn of Internet of Things (IoT) era, the chip industry needs adjustments towards ultra-low-power circuits and systems. In this thesis, energy-efficient Micro-/Nano-electromechanical (M/NEM) relays are introduced, their non-leaking property and abrupt switch ON/OFF characteristics are studied, and designs and applications in the implementation of ultra-low-power integrated circuits and systems are explored. The proposed designs compose of core building blocks for any functional microprocessor, for instance, fundamental logic gates; arithmetic adder circuits; sequential latch and flip-flop circuits; input/output (I/O) interface data converters, including an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC); system-level power management DC-DC converters and energy management power gating scheme. Another contribution of this thesis is the study of device non-ideality and variations in terms of functionality of circuits. We have thoroughly investigated energy-efficient approximate computing with non-ideal transistors and relays for the next generation of ultra-low-power VLSI systems.

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Power consumption and battery life are of critical importance for medical implant devices. For this reason, devices for Wireless Body Area Network (WBAN) applications must consume very little power. To save power, it is desirable to turn off or put to sleep a device when not in use. However, a transceiver, which is the most power hungry block of a wireless sensor node, needs to listen for the incoming signal continuously. An alternative scheme, is to listen for the incoming signal at a predetermined internal, which saves power at the cost of increased latency. Another and more sophisticated scheme is to provide a wake-up receiver, which listens for the incoming signal continuously, and upon detection of an incoming signal, it wakes the primary transceiver up. A wake-up receiver is typically simple and dissipates little power to make the scheme useful. This thesis proposes a low-power wake-up receiver, which listens for a wake-up signal, identifies the target node, and wakes up the primary receiver only when that specific node is called upon. When a wake up signal is transmitted to all of the nodes on a network, our wake-up receiver allows all the nodes on a network except the targeted node to remain asleep to save power. Several wake-up receiver topologies have been proposed. This work uses a passive Cockcroft-Walton multiplier circuit as an RF envelope detector followed by a simple detector circuit. A novel serial code detector is then used to decode the pulse width modulated input signal to wake-up the designated node. A passive RF front end and simple decoding circuit reduce power consumption substantially at the cost of low sensitivity. The sensitivity of the wake-up receiver can be improved though the addition of an RF amplifier, but at the cost of increased power consumption. / Master of Science