No description available.

This work is a first step towards a long-term goal of understanding computations occurring in the brain and using those principles to make more efficient machines. The traditional computing paradigm calls for using digital supercomputers to simulate large scale brain-like neural networks resulting in large power consumption which limits scalability or model detail. For example, IBM's digital simulation of a cat brain with simplistic neurons and synapses consumes power equivalent to that of a thousand houses! Instead of digital methods, this work uses analog processing concepts to develop scalable, low-power silicon models of neurons which have been shown to be around ten thousand times more power efficient. This has been achieved by modeling the dynamical behavior of Hodgkin-Huxley (H-H) or Morris-Lecar type equations instead of modeling the exact equations themselves. In particular, the two silicon neuron designs described exhibit a Hopf and a saddle-node bifurcation. Conditions for the bifurcations allow the identification of correct biasing regimes for the neurons. Also, since the hardware neurons compute in real time, they can be used for dynamic clamp protocols in addition to computational experiments. To empower this analog implementation with the flexibility of a digital simulation, a family of field programmable analog array (FPAA) architectures have been developed in 0.35 um CMOS that provide reconfigurability in the network of neurons as well as tunability of individual neuron parameters. This programmability is obtained using floating-gate (FG) transistors. The neurons are organized in blocks called computational analog blocks (CAB) which are embedded in a programmable switch matrix. An unique feature of the architecture is that the switches, being FG elements, can be used also for computation leading to more than 50,000 analog parameters in 9 sq. mm. Several neural systems including central pattern generators and coincidence detectors are demonstrated. Also, a separate chip that is capable of implementing signal processing algorithms has been designed by modifying the CAB elements to include transconductors, multipliers etc. Several systems including an AM demodulator and a speech processor are presented. An important contribution of this work is developing an architecture for programming the FG elements over a wide dynamic range of currents. An adaptive logarithmic transimpedance amplifier is used for this purpose. This design provides a general solution for wide dynamic range current measurement with a low power dissipation and has been used in imaging chips too. A new generation of integrated circuits have also been designed that are 25 sq. mm in area and contain several new features including adaptive synapses and support for smart sensors. These designs and the previous ones should allow prototyping and rapid development of several neurally inspired systems and pave the path for the design of larger and more complex brain like adaptive neural networks.

Submitted by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:21Z No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:37Z (GMT) No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:56Z (GMT) No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Made available in DSpace on 2016-11-25T15:39:56Z (GMT). No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) Previous issue date: 2016-04-18 / This work presents a study on the behavior and effectiveness of different Fixed-Pattern Noise (FPN) reduction techniques applied to different pixel topologies operating in logarithmic mode. The purpose of such study is the establishment of a consistent way to perform fair cross comparison of the effectiveness of different FPN attenuation techniques applied to pixels with different topologies and designed in the same technological node, and thus establish judgment criteria for determining which topology will be most suitable for implementation of an image sensor operating in logarithimic mode. Investigations of the effectiveness of two similar FPN reduction techniques applied to four different pixel topologies were performed through Monte Carlo simulations. The analyses of results of output signal swing, total and residual FPN, signal-to-distortion ratio, power consumption and fill factor are able to demonstrate which pixel topologies yield better results in each of these criteria. Such results provide valuable data that allows a more concise decision on which pixel topology and FPN reduction technique to choose in the design of an imager array with wide dynamic range. / Este trabalho apresenta um estudo sobre o comportamento e eficácia de diferentes técnicas de redução de ruído de padrão fixo, do inglês fixed-pattern noise (FPN), aplicadas a diferentes topologias de pixel operando em modo logarítmico. A finalidade deste estudo é o estabelecimento de um meio consistente para realizar comparação cruzada imparcial da eficácia de diferentes técnicas de redução de FPN aplicadas a pixeis com diferentes topologias e projetados sob o mesmo rótulo tecnológico, e assim estabelecer critérios de julgamento que permitam determinar qual topologia será a mais adequada para implementação de um sensor de imagem operando em modo logarítmico. Investigações da eficácia de duas técnicas de redução de FPN similares aplicadas a quatro diferentes topologias de pixel foram realizadas através de simulações Monte Carlo. As análises dos resultados de excursão do sinal de saída, FPN total e residual, razão de distorção do sinal, consumo de energia e fator de preenchimento são capazes de demonstrar que topologias de pixel produzem melhores resultados em cada um destes critérios. Tais resultados proporcionam dados valiosos que permitem uma mais concisa decisão sobre qual topologia de pixel e técnica de redução de FPN escolher no projeto de um sensor de imagem com largo alcance dinâmico.

No description available.

Within the realm of biosensing, DNA analysis has become an indispensable research tool in medicine, enabling the investigation of relationships among genes, proteins, and drugs. Conventional DNA microarray technology uses multiple lasers and complex optics, resulting in expensive and bulky systems which are not suitable for point-of-care medical diagnostics. The immobilization of DNA probes across the microarray substrate also results in substantial spatial variation. To mitigate the above shortcomings, this thesis presents a set of techniques developed for the CMOS image sensor for point-of-care spectrally-multiplexed fluorescent DNA sensing and other fluorescence biosensing applications. First, a CMOS tunable-wavelength multi-color photogate (CPG) sensor is presented. The CPG exploits the absorption property of a polysilicon gate to form an optical filter, thus the sensor does not require an external color filter. A prototype has been fabricated in a standard 0.35μm digital CMOS technology and demonstrates intensity measurements of blue (450nm), green (520nm), and red (620nm) illumination. Second, a wide dynamic range CMOS multi-color image sensor is presented. An analysis is performed for the wide dynamic-range, asynchronous self-reset with residue readout architecture where photon shot noise is taken into consideration. A prototype was fabricated in a standard 0.35μm CMOS process and is validated in color light sensing. The readout circuit achieves a measured dynamic range of 82dB with a peak SNR of 46.2dB. Third, a low-power CMOS image sensor VLSI architecture for use with comparator based ADCs is presented. By eliminating the in-pixel source follower, power consumption is reduced, compared to the conventional active pixel sensor. A 64×64 prototype with a 10μm pixel pitch has been fabricated in a 0.35μm standard CMOS technology and validated experimentally. Fourth, a spectrally-multiplexed fluorescence contact imaging microsystem for DNA analysis is presented. The microsystem has been quantitatively modeled and validated in the detection of marker gene sequences for spinal muscular atropy disease and the E. coli bacteria. Spectral multiplexing enables the two DNA targets to be simultaneously detected with a measured detection limit of 240nM and 210nM of target concentration at a sample volume of 10μL for the green and red transduction channels, respectively.

Within the realm of biosensing, DNA analysis has become an indispensable research tool in medicine, enabling the investigation of relationships among genes, proteins, and drugs. Conventional DNA microarray technology uses multiple lasers and complex optics, resulting in expensive and bulky systems which are not suitable for point-of-care medical diagnostics. The immobilization of DNA probes across the microarray substrate also results in substantial spatial variation. To mitigate the above shortcomings, this thesis presents a set of techniques developed for the CMOS image sensor for point-of-care spectrally-multiplexed fluorescent DNA sensing and other fluorescence biosensing applications. First, a CMOS tunable-wavelength multi-color photogate (CPG) sensor is presented. The CPG exploits the absorption property of a polysilicon gate to form an optical filter, thus the sensor does not require an external color filter. A prototype has been fabricated in a standard 0.35μm digital CMOS technology and demonstrates intensity measurements of blue (450nm), green (520nm), and red (620nm) illumination. Second, a wide dynamic range CMOS multi-color image sensor is presented. An analysis is performed for the wide dynamic-range, asynchronous self-reset with residue readout architecture where photon shot noise is taken into consideration. A prototype was fabricated in a standard 0.35μm CMOS process and is validated in color light sensing. The readout circuit achieves a measured dynamic range of 82dB with a peak SNR of 46.2dB. Third, a low-power CMOS image sensor VLSI architecture for use with comparator based ADCs is presented. By eliminating the in-pixel source follower, power consumption is reduced, compared to the conventional active pixel sensor. A 64×64 prototype with a 10μm pixel pitch has been fabricated in a 0.35μm standard CMOS technology and validated experimentally. Fourth, a spectrally-multiplexed fluorescence contact imaging microsystem for DNA analysis is presented. The microsystem has been quantitatively modeled and validated in the detection of marker gene sequences for spinal muscular atropy disease and the E. coli bacteria. Spectral multiplexing enables the two DNA targets to be simultaneously detected with a measured detection limit of 240nM and 210nM of target concentration at a sample volume of 10μL for the green and red transduction channels, respectively.