Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2008/05/09). Includes bibliographical references.

Thesis (Ph.D.). / Written for the School of Computer Science. Title from title page of PDF (viewed 2008/02/12). Includes bibliographical references.

Tato diplomová práce se zabývá návrhem IP bloku pro diskrétní kosinovou transformaci. V~teoretické části jsou shrnuty algoritmy pro výpočet diskrétní kosinové transformace a diskutována jejich použitelnost v~hardwaru. Zvolený algoritmus pro hardwarovou implementaci je modelován v jazyce C. Poté je popsán na RTL úrovni, verifikován a je provedena syntéza v~technologii TSMC 65 nm. Hardwarová implementace je poté zhodnocena s ohledem na datovou propustnost, plochu, rychlost and spotřebu.

No description available.

RISC-V is an open-source instruction-set architecture (ISA) forming the basis of thousands of commercial and experimental microprocessors. The Scalar Cryptography extension ratified in December 2021 added scalar instructions that target common hashing and encryption algorithms, including SHA2 and AES. The next step forward for the RISC-V ISA in the field of cryptography and digital security is the development of vector cryptography instructions. This thesis examines if it is viable to add vector implementations of existing RISC-V scalar cryptography instructions to the existing vector instruction format, and what improvements they can make to the execution of SHA2 and AES algorithms. Vector cryptography instructions vaeses, vaesesm, vaesds, vaesdsm, vsha256sch, and vsha256hash are proposed to optimize AES encryption and decryption, SHA256 message scheduling, and SHA256 hash rounds, with pseudocode, assembly examples, and a full 32-bit instruction format for each. Both algorithms stand to benefit greatly from vector instructions in reduction of computation time, code length, and instruction memory utilization due to large operand sizes and frequently repeated functions. As a proof of concept for the vector cryptography operations proposed, a full vector-based AES-128 encryption and SHA256 message schedule generation are performed on the 32-bit RISC-V Ibex processor and 128-bit Vicuna Vector Coprocessor in the Vivado simulation environment. Not counting stores or loads for fair comparison, the new Vector Cryptography extension completes a full encryption round in a single instruction compared to sixteen with the scalar extension, and can generate eight SHA256 message schedule double-words in a single instruction compared to the forty necessary on the scalar extension. These represent a 93.75% and 97.5% reduction in required instructions and memory for these functions respectively, at a hardware cost of 19.4% more LUTs and 1.44% more flip-flops on the edited Vicuna processor compared to the original.

No description available.

The security of service, confidential data, and intellectual property are threatened by physical attacks, which usually include reading and tampering the data. In many cases, attackers can have access to the tools and equipment that can be used to read the memory or corrupt it, either by invasive or non-invasive means. The secret keys used by cryptographic algorithms are usually stored in a memory. Physical unclonable functions (PUFs) are promising to deal with such vulnerabilities since, in the case of PUFs, the keys are generated only when required and do not need to be stored on a powered-off chip. PUFs use the inherent variations in the manufacturing process to generate chip-unique output sequences (response) to a query (challenge). These variations are random, device-unique, hard to replicate even by the same manufacturer using identical process, equipment and settings, and supposed to be static, making the PUF an ideal candidate for generation of cryptographic keys. This thesis work focuses on a delay-based PUF called arbiter PUF. It utilizes the intrinsic propagation delay differences of two symmetrical paths. In this work, an arbiter PUF implemented in Altera FPGA has been evaluated. The implementation includes Verilog HDL coding, placement and routing, and the communication methods between PC and FPGAs to make testing more efficient. The experimental results were analyzed based on three criteria, reliability, uniqueness, and uniformity. Experimental results show that the arbiter PUF is reliable with respect to temperature variations, although the bit error rate increases as the temperature difference becomes larger. Results also reveal that the uniqueness of the PUFs on each FPGA device is particularly low but on the other hand, the proportions of different response bits are uniform after symmetric routing is performed. / Tjänstens säkerhet, konfidentiella uppgifter och immateriell egendom hotas av fysiska attacker, som vanligtvis inkluderar läsning och manipulering av uppgifterna. I många fall kan angripare ha tillgång till de verktyg och utrustning som kan användas för att läsa minnet eller skada det , antingen med invasiva eller icke-invasiva medel. De hemliga nycklarna som används av kryptografiska algoritmer lagras vanligtvis i ett minne. Fysiska okonabla funktioner (PUF: er) lovar att hantera sådana sårbarheter eftersom, för PUF: er, nycklarna genereras endast när det behövs och inte behöver lagras på ett avstängd chip. PUF: er använder de inneboende variationerna i tillverkningsprocessen för att generera chip-unika utgångssekvenser (svar) på en fråga (utmaning). Dessa variationer är slumpmässiga, enhetsunika, svårt att kopiera till och med av samma tillverkare med identisk process, utrustning och inställningar, och antas vara statisk, vilket gör PUF till en idealisk kandidat för generering av kryptografiska nycklar. Detta avhandlingsarbete fokuserar på en fördröjningsbaserad PUF som kallas arbiter PUF. Den använder de inneboende utbredningsfördröjningsskillnaderna för två symmetriska vägar. I detta arbete har en arbiter PUF implementerad i Altera FPGA utvärderats. Implementeringen inkluderar Verilog HDLkodning, placering och routing och kommunikationsmetoderna mellan PC och FPGA för att effektivisera testningen. De experimentella resultaten analyserades baserat på tre kriterier, tillförlitlighet, unikhet och enhetlighet. Experimentella resultat visar att arbiter PUF är tillförlitlig med avseende på temperaturvariationer, även om bitfelfrekvensen ökar när temperaturdifferensen blir större. Resultaten avslöjar också att unikheten hos PUF: erna på varje FPGA-enhet är särskilt låg men å andra sidan är proportionerna av olika svarbitar enhetliga efter att symmetrisk dirigering har utförts.

Les travaux de cette thèse s’inscrivent dans un projet de grande envergure, le projet 3D-IDEAS, financé par l’ANR. Le but de ce projet est d’établir la chaîne complète de l’intégration de circuits en technologie 3D. Les densités de puissance dans ces circuits sont telles que les problèmes liés à la température – électromigration, désappariement des courants et tensions de polarisation, etc. – sont susceptibles de remettre en cause la conception du circuit. Le coût élevé de la fabrication de ces circuits oblige le concepteur à valider le comportement électrothermique des circuits préalablement à l’envoi en fabrication. Pour répondre à ce besoin, un simulateur électrothermique précis et fiable doit être à disposition. En outre, en raison de la complexité extrême de ces circuits, il est judicieux que ce simulateur soit compatible avec l’approche de modélisation haut niveau. L’objectif de cette thèse est de développer un tel simulateur. La solution proposée intègre ce simulateur dans un environnement de développement CAO pour circuit intégré standard, Cadence®. La contrainte sur la précision des résultats nous a amené à développer une nouvelle méthodologie spécifique à la modélisation électrothermique haut-niveau. Ce manuscrit comporte deux grandes parties. Dans la première, la démarche adoptée pour concevoir le simulateur est détaillée. Ensuite, dans la seconde partie, le fonctionnement du simulateur ainsi que la méthode de modélisation haut-niveau mise en place sont présentées, puis validées. / The work of this thesis is part of a larger project, the project 3D-IDEAS, funded by the ANR. The purpose of this project is to establish the complete chain of integrated circuits built upon 3D technology. Power densities in these circuits are exacerbated, thus problems related to temperature, such as electromigration, mismatch of bias currents and voltages, etc., arise and might have critical effects on the circuit behavior. The high cost of these circuits requires the designer to validate the electro-thermal behavior of circuits prior to manufacturing. To meet this need, an accurate and reliable electro-thermal simulator should be available. Moreover, due to the extreme complexity of these circuits, it is wise for such a simulator to be compliant with high level modeling approach. The objective of this thesis is to develop such a simulator. The proposed solution integrates the simulator in the broadly used CAD environment for integrated circuits Cadence®. The need of accurate results led us to develop a new methodology specific to high level electro-thermal modeling. This manuscript is split in two major parts. In the first one, the approach to implement the simulator is detailed. Then, in the second part, the operation principle of the simulator and the modeling method implementation are detailed and validated.

The growing number of players in Massively Multiplayer Online games puts a heavy load on the network infrastructure and the general-purpose CPU of the game servers. A game server’s network stack processing needs equal treatment to the game-related processing ability. It is a fact that the networkcommunication tasks on the CPU reach the same order of magnitude as the game-related tasks, and the computing capability of the CPU can be a factor that limits the maximum number of players. Therefore, CPU offloading is becoming vital. FPGAs play an essential role in dedicated computation and network communication due to their superiority in flexibility and computation-oriented efficiency. Thus, an FPGA can be a good hardware platform to implement a network stack to replace the CPU in processing the network computations. However, most commercial and open-source network stack IPs support only one or few connections. This thesis project explores a network server on FPGA, implemented in RTL, that can handle multiple connections, specialized in the TCP protocol. The design in this project adds a cached memory hierarchy that provides a filter against port numbers of multiple connections from the same application and an Application Layer Controller, based on an open-source Ethernet, to increase the number of TCP connections further. A proof of concept was built, and its performance was tested. As a result, the TCP server on the FPGA was designed to handle a maximum of 40 configurable connections, but only 25 connections could be maintained during operation due to operational latency constraints. This FPGA server solution provides a latency of 1 ms in LAN. The babbling idiot and out-of-order packet transfer tests from clientswere also performed to guarantee robustness. During testing, poor performance in Packet Loss and Packet Error Handling was noted. In the future, this issue needs to be addressed. In addition, further investigations of methods for expanding the cache need to be done to allow handling more clients. / Det växande antalet spelare i Massively Multiplayer Online-spel belastar nätverksinfrastrukturen och spelservrarnas CPU:er. En spelservers förmåga att bearbeta nätverksstacken måste behandlas lika med den spelrelaterade bearbetningsförmågan. Det är ett faktum att nätverkskommunikationsuppgifterna på processorn når samma storleksordning som de spelrelaterade uppgifterna, och processorns beräkningsförmåga kan vara en faktor som begränsar det maximala antalet spelare. Därför blir avlastning av CPU-viktig. FPGA:er spelar en viktig roll i dedikerad beräkning och nätverkskommunikation på grund av dess överlägsenhet vad gäller flexibilitet och beräkningsorienterad effektivitet. Således kan en FPGA vara en bra hårdvaruplattform för att implementera en nätverksstack, för att ersätta CPU:n vid bearbetning av nätverksberäkningsarna. Men, de flesta kommersiella och öppna källkodsnätverksstack- IP:er stöder dock bara en eller ett fåtal anslutningar. Detta examensarbete utforskar en nätverksserver på FPGA, implementerad mha RTL, som kan hantera flera anslutningar, specialiserad på TCP-protokollet. Designen i detta projekt lägger till en cachad minneshierarki som ger ett filter mot portnummer för flera anslutningar från samma applikation och en Application Layer Controller, baserad på öppen källkod för Ethernet, för att öka antalet TCP-anslutningar ytterligare. Ett proof of concept byggdes och dess prestanda testades. Som ett resultat designades TCP-servern på FPGA:n att kunna hantera maximalt 40 konfigurerbara anslutningar, men endast 25 anslutningar kunde bibehållas under drift på grund av driftsfördröjningar. Denna FPGA-serverlösning ger en latens på 1 ms i LAN. Tester inkluderande den babblande idioten och out-of-order paketöverföring från klienter utfördes också för att garantera robusthet. Under testningen noterades dålig prestanda i paketförlust och paketfelshantering. I framtiden måste denna fråga åtgärdas. Dessutom behöver ytterligare undersökningar av metoder för att utöka cachen göras för att kunna hantera fler klienter.

Master of Science / Department of Electrical and Computer Engineering / Don M. Gruenbacher / As semiconductor technologies advance, the smallest feature sizes that can be fabricated get smaller. This has led to the development of high density FPGAs capable of supporting high clock speeds, which allows for the implementation of larger more complex designs on a single chip. Over the past decade the technology market has shifted toward mobile devices with low power consumption at or near the top of design considerations. By reducing power consumption in FPGAs we can achieve greater reliability, lower cooling cost, simpler power supply and delivery, and longer battery life. In this thesis, FPGA technology is discussed for the design and commercial implementation of low power systems as compared to ASICs or microprocessors, and a few techniques are suggested for lowering power consumption in FPGA designs. The objective of this research is to implement some of these approaches and attempt to design a low power signal acquisition module. Designing for low power consumption without compromising performance requires a power-efficient FPGA architecture and good design practices to leverage the architectural features. With various power conservation techniques suggested for every stage of the FPGA design flow, the following approach was used in the design process implementation: the switching activity is addressed in the design entry, and synthesis level and software tools are utilized to get an initial estimate of and optimize the design’s power consumption. Finally, the device choice is made based on its features that will enhance the optimization achieved in the previous stages; it is configured and real time board level power measurements are made to verify the implementation’s efficacy