Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear dependencies present in the LFSM generated test-bit sequences adversely affect the resultant fault coverage in two-dimensional scan designs. In this work, we present methods that improve the resultant fault coverage in two-dimensional scan designs through the minimization of linear dependencies. Currently, metric of channel separation and matrix-based metric are used in order to estimate linear dependencies in a CUT. When the underlying sub-circuit (cone) structure of a CUT is available, the matrix-based metric can be used more effectively. Fisrt, we present two methods that use matrix-based metric and minimize the overall linear dependencies in a CUT through explicitly minimizing linear dependencies in the highest number of underlying cones of the CUT. The first method minimizes linear dependencies in a CUT through the selection of an appropriate LFSM structure. On the other hand, the second method synthesizes a phase shifter for a specified LFSM structure such that the overall linear dependencies in a CUT are minimized. However, the underlying structure of a CUT is not always available and in such cases the metric of channel separation can be used more effectively. The metric of channel separation is an empirical measure of linear dependencies and an ad-hoc large channel separation is imposed between the successive scan chains of a two-dimensional scan design in order to minimize the linear dependencies. Present techniques use LFSMs with additional phase shifters (LFSM/PS) as PRPGs in order to obtain desired levels of channel separation. We demonstrate that Generalized LFSRs (GLFSRs) are a better choice as PRPGs compared to LFSM/PS and obtain desired levels of channel separations at a lower hardware cost than the LFSM/PS. Experimental results corroborate the effectiveness of the proposed methods through increased levels of the resultant fault coverage in two-dimensional scan designs.

Thermal management has emerged as an important design issue in a range of designs from portable devices to server systems. Internal thermal sensors are an integral part of such a management system. Process variations in CMOS circuits cause accuracy problems for thermal sensors which can be fixed by calibration tables. Stand-alone thermal sensors are calibrated to fix such problems. However, calibration requires going through temperature steps in a tester, increasing test application time and cost. Consequently, calibrating thermal sensors in typical digital designs including mainstream desktop and notebook processors increases the cost of the processor. This creates a need for design of thermal sensors whose accuracy does not vary significantly with process variations. Other qualities desired from thermal sensors include low area requirement so that many of them maybe integrated in a design as well as low power dissipation, such that the sensor itself does not become a significant source of heat. In this work, we developed a process variation tolerant thermal sensor design with (i) active compensation circuitry and (ii) signal dithering based self calibration technique to meet the above requirements in 32nm technology. Results show that we achieve 3ºC temperature accuracy, with a relatively small design which compares well with designs that are currently used.

As CMOS technology scaling is fast approaching its fundamental limits, several new nano-electronic devices have been proposed as possible alternatives to MOSFETs. Research on emerging devices mainly focusses on improving the intrinsic characteristics of these single devices keeping the overall integration approach fairly conventional. However, due to high logic complexity and wiring requirements, the overall system-level power, performance and area do not scale proportional to that of individual devices. Thereby, we propose a fundamental shift in mindset, to make the devices themselves more functional than simple switches. Our goal in this thesis is to develop a new nanoscale fabric paradigm that enables realization of arbitrary logic functions (with high fan-in/fan-out) more efficiently. We leverage on non-equilibrium spin wave physical phenomenon and wave interference to realize these elementary functions called Spin Wave Functions (SPWFs). In the proposed fabric, computation is based on the principle of wave superposition. Information is encoded both in the phase and amplitude of spin waves; thereby providing an opportunity for compressed data representation. Moreover, spin wave propagation does not involve any physical movement of charge particles. This provides a fundamental advantage over conventional charge based electronics and opens new horizons for novel nano-scale architectures. We show several variants of the SPWFs based on topology, signal weights, control inputs and wave frequencies. SPWF based designs of arithmetic circuits like adders and parallel counters are presented. Our efforts towards developing new architectures using SPWFs places strong emphasis on integrated fabric-circuit exploration methodology. With different topologies and circuit styles we have explored how capabilities at individual fabric components level can affect design and vice versa. Our estimates on benefits vs. 45nm CMOS implementation show that, for a 1-bit adder, up to 40x reduction in area and 228x reduction in power is possible. For the 2-bit adder, results show that up to 33x area reduction and 222x reduction in power may be possible. Building large scale SPWF-based systems, requires mechanisms for synchronization and data streaming. In this thesis, we present data streaming approaches based on Asynchronous SPWFs (A-SPWFs). As an example, a 32-bit Carry Completion Sensing Adder (CCSA) is shown based on the A-SPWF approach with preliminary power, performance and area evaluations.

Weather monitoring and forecasting systems have witnessed rapid advancement in recent years. However, one of the main challenges faced by these systems is poor coverage in lower atmospheric regions due to earth's curvature. The Engineering Research Center for the Collaborative Adaptive Sensing of the Atmosphere (CASA) has developed a dense network of small low-power radars to improve the coverage of weather sensing systems. Traditional, mechanically-scanned antennas used in these radars are now being replaced with high-performance electronically-scanned phased-arrays. Phased-Array radars, however, require large number of active microwave components to scan electronically in both the azimuth and elevation planes, thus significantly increasing the cost of the entire radar system. To address this issue, CASA has designed a "Phase-Tilt" radar, that scans electronically in azimuth and mechanically in elevation. One of the core components of this system is the Phased-Array controller or the Array Formatter. The Array Formatter is a Field Programmable Gate Array (FPGA)-based master controller that translates user commands from a computer to control and timing signals for the radar system. The objective of this thesis is to design and test an FPGA-based Array Formatter for CASA's Phase-Tilt radar system.

Present research into critical embedded control systems tends to focus on the computational elements and largely ignore the link between the computational and physical elements. This link is very important since the computational capability of the computer can greatly affect the performance and dynamics of the system it controls. The control computer is in the feedback loop of control systems and contributes to feedback delay in addition to already existing mechanical delays. While mechanical delays are compensated in control design, variable computational delays cause system to underperform in its intended physical behavior and impose a cost in terms of fuel or time. For this reason, the scheduler in a real-time operating systems should not focus only on the task deadlines, but also on efficient scheduling which minimizes the effect of computational delay on the controlled plant. The proposed work provides a systematic framework to manage and evaluate the implications of computational delay in vehicles. The work also includes cost sensitive real-time control task scheduling heuristics and Dynamic Voltage Scaling (DVS) for better energy/thermal control. We show through simulations that our heuristic achieves a significant improvement in cost over the traditional real-time scheduling algorithm Earliest Deadline First (EDF) and show that it can adjust according to energy constraints imposed on the system.

Localized heating leads to generation of thermal Hotspots that affect performance and reliability of an Integrated Circuit(IC). Functional workloads determine the locations and temperature of hotspots on a die. Programs are classified into phases based on program execution profile. During a phase, spatial power dissipation pattern of an application remains unchanged. In this thesis, we present a systematic approach for developing a synthetic workload from a functional workload to create worst case temperature of a target hotspot in 2D and 3D IC. These synthetic workload are designed to create thermal stress patterns, which would help in characterizing the thermal characteristics of micro architecture to worst case temperature transient which is an important problem in Industry. Our approach is based on the observation that, worst case temperature at a particular location in 2 D IC is determined not only by the current activity in that region, but also by the past activities in the surrounding regions. Therefore, if the surrounding areas were “pre-heated” with a different workload, then the target region may become hotter due to slower rate of lateral heat dissipation Similarly in case of 3D IC, the workload applied to each of the dies in 3D IC keeps on changing continuously, thus the hotspot could be found in any of the stacked layers. Thus the creation of localized hotspot at a particular location in a stacked 3D IC layer depends not only on the present activity at that location but also on the previous activity in the surrounding region and also on the activity of layers below it. Accordingly, (i) we develop a wavelet-based canonical spatio-temporal heat dissipation model for program traces, and use (ii) a novel Integer Linear Programming (ILP) formulation to rearrange program phases to generate target worst case hotspot temperature in 2D and 3D IC. We apply this formulation to target another well-known problem of (iii) maximizing temperature between a pair of co-ordinates in an IC. Experimental results show that by taking the spatio-temporal effect into account and with dynamic phase change behavior, we could raise temperature of a hotspot higher than what is possible otherwise. ICs are often tested at worst-case system operating conditions to assure that, all ICs shipped will function properly in the end system. Thus hotspot temperature maximization is an important in design verification and testing.

Nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. These fabrics employ unconventional manufacturing techniques like Nano-imprint lithography or Super-lattice Nanowire Pattern Transfer to produce ultra-dense nano-structures. However, one key challenge that has received limited attention is the interfacing of unconventional/self-assembly based approaches with conventional CMOS manufacturing to build integrated systems. We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules to build a reliable nanowire-CMOS 3-D integrated fabric called N3ASICs with no new manufacturing constraints. In N3ASICs active devices are formed on a dense semiconductor nanowire array and standard area distributed pins/vias, metal interconnects route signals in 3D. The proposed N3ASICs fabric is fully described and thoroughly evaluated at all design levels. Novel nanowire based devices are envisioned and characterized based on 3D physics modeling. Overall N3ASICs fabric design, associated circuits, interconnection approach, and a layer-by-layer assembly sequence for the fabric are introduced. System level metrics such as power, performance, and density for a nanoprocessor design built using N3ASICs were evaluated and compared against a functionally equivalent CMOS design. We show that the N3ASICs version of the processor is 3X denser and 5X more power efficient for a comparable performance than the 16-nm scaled CMOS version without any new/unknown-manufacturing requirement. Systematic yield implications due to mask overlay misalignment have been evaluated. A partitioning approach to build complex circuits has been studied.

This thesis presents time difference (TD) circuits that are important for measuring fluorescence lifetime, building LIDAR systems, and optimizing digital systems. The contribution of this thesis is to present a systematic organization of TD circuits and to present novel designs for digital-to-time conversion (DTC) and time-to-digital conversion (TDC). Four basic time difference circuits are presented: TD adder, arbiter, time-difference MUX, and time-difference memory. Specifications, symbols, and multiple circuit implementations are presented for each block. Then the basic blocks are combined to form two compound blocks: DTC and TDC. Novel designs are presented for both blocks along with detailed simulation results. The DTC was fabricated in TSMC’s 0.35um high-voltage process. A printed circuit board was designed to interface the DTC chip to a computer and test instruments. The DTC demonstrated 80ps resolution.

The Monterey Bay Aquarium Research Institute (MBARI) established the Free Ocean Carbon Enrichment (FOCE) experiment to study the long-term effects of decreased ocean pH levels by developing in-situ platforms [1]. Deep FOCE (dpFOCE) was the first platform, which was deployed in 950 meters of water in Monterey Bay. After the conclusion of dpFOCE, MBARI developed an open source shallow water FOCE (swFOCE) platform located at around 250 meter of water to facilitate worldwide shallow water experiments on FOCE [1][2]. A shallow water platform can be more ubiquitous than a deep-water platform as shallow water instruments are less expensive (as it does not have to be designed to withstand the pressure at deep ocean depths) and more easily deployed (they can be deployed right along the coast). The swFOCE experiment is an open source platform, and MBARI has made the plans available online to anyone interested in studying shallow water carbon enrichment. There is a gateway node what is connected to four sensor nodes within the swFOCE. In order to test the sensor node individually, an idea of designing an Oceanographic Instrument Simulator is purposed. The Oceanographic instrument simulator (OIS), described in this paper provides the means for MBARI engineers to test the swFOCE platform without attaching the numerous and expensive oceanographic instruments. The Oceanographic Instrument Simulator simulates the various scientific instruments that could be deployed in an actual experiment. The Oceanographic Instrument Simulator (OIS) system includes the designed circuit board, Arduino Due and an SD Card shield. The designed circuit board will be connected to a computer through a USB cable, and be connected to MBARI’s swFOCE sensor node through a serial connection. When a query is given from the sensor node, the Arduino Due will parse the data given from the sensor node, search through the pre-installed data in the SD card and return the appropriate data back to the sensor node. A user can also manually set up the input current through a computer terminal window to control the simulated signals from the PCB.

Globally-Asynchronous, Locally-Synchronous (GALS) design techniques employ the finer points of synchronous and asynchronous design methods to eliminate problems arising due to clock distribution, power dissipation, and large area over head. With the recent rise in the demand for System-on-a-Chip (SoC) designs, global clock distribution and power dissipation due to clock distribution are inevitable. In order to reduce/eliminate the effects of the global clock in synchronous designs and large area overhead in asynchronous designs, an alternative approach would be to utilize GALS design techniques. Not only do GALS designs eliminate the issue of using a global clock, they also have smaller area overhead when compared to purely asynchronous designs. Among the various GALS design approaches proposed till date, this thesis focuses on the working and implementation of Asynchronous Wrapper designs proposed by Muttersbach et al., in [1, 2]. This thesis specifically addresses different approaches to incorporate the wrappers in VLSI circuits, rather than discussing the efficiency and viability of GALS design techniques over purely synchronous or asynchronous approaches. It has been proven by researchers [3] that GALS design approaches bring down power consumption due to the elimination of the global clock by small amounts, but there is also a drop in performance. Since the goal of this thesis is to introduce the reader to GALS design techniques and not prove their efficiency, it is out of the scope of this thesis to validate the results shown in [3]. In our aim to introduce the reader to GALS design techniques, we first provide a comparison of synchronous and asynchronous design approaches, and then discuss the need for GALS design approaches. We will then address issues affecting GALS such as metastability, latency, flow control, and local clock alteration. After familiarizing the reader with the issues affecting GALS, we will then discuss various GALS design techniques proposed till date. We show the use of asynchronous FIFOs and asynchronous wrappers to realize GALS modules. Two wrapper design approaches are discussed: one being the asynchronous wrapper design proposed by Carlsson et al., in [4], and the other being the asynchronous wrapper design proposed in [1, 2]. An in-depth discussion and analysis of the wrapper design approach proposed in [1, 2] is provided based on the state transition graphs (STGs) that characterize the port-controller AFSMs. Various data transfer channel configurations that incorporate the wrapper port-controllers are designed and realized through VHDL codes, with their functioning verified through simulation results. Design examples showing the working of asynchronous wrappers to achieve point-to-point, synchronous-synchronous and synchronous-asynchronous data communication are provided. Finally, a design example to achieve multi-point data communication is realized. This example incorporates a previously proposed idea. We provide a modification to this idea by designing an arbiter that arbitrates between two separate requests coming into a multi-input port. Through the above design examples, the functionality and working of GALS asynchronous wrappers are verified, and recommendations for modifications are made to achieve flexible multi-point data communication.