Orientador: Nobuo Oki / Banca: Cláudio Kitano / Banca: Márcio Barbosa Lucks / Resumo: Referências de tensão integradas com baixa sensibilidade à temperatura, tensão de a- limentação e eventos transitórios são componentes críticos na maioria dos circuitos integra- dos. Neste trabalho, além das restrições costumeiras, foi adicionada a preocupação com a in- terferência eletromagnética a qual vem ganhando muita importância devido a crescente polui- ção eletromagnética no ambiente. Assim, neste trabalho, propõe-se o projeto de uma referên- cia de tensão tipo bandgap com baixa susceptibilidade a interferência eletromagnética (EMI). O projeto deste circuito baseia-se na soma de duas correntes (referência de tensão baseada em corrente), uma com coeficiente complementar a temperatura absoluta (CTAT) e outra com coeficiente proporcional à temperatura absoluta (PTAT), aplicada sobre um resistor. Neste projeto, a susceptibilidade a interferência eletromagnética de uma referência de tensão band- gap é estudada por meio de simulação. Projetada para ser fabricada com a tecnologia CMOS 0,35 μm da AMS (Autriamicrosystems), a referência forneceu uma tensão de referência está- vel de 1,354 V em sua saída operando normalmente na faixa de temperatura de -40 a 150oC. Quando submetido à EMI, o circuito exibiu apenas 24,7 mV (quando filtros capacitivos são incluído) de offset induzido, para um sinal de interferência variando de 150 kHz a 1 GHz / Abstract: Integrated voltage references with low sensitivity to temperature, supply voltage and transient events are critical requirements in the most of integrated circuits. In this work, be- sides the usual restrictions, was added to concern with electromagnetic interference which is gaining much importance due to increasing electromagnetic pollution on the environment. So, in this work, proposes the design of a bandgap voltage reference with low susceptibility to electromagnetic interference (EMI) is proposed. The design of the circuit is based on the sum of two currents (current-based voltage reference), one with coefficient complementary to ab- solute temperature (CTAT) and the other with coefficient proportional to absolute temperature (PTAT) into a resistor. In this work, the susceptibility to electromagnetic interference in a bandgap voltage reference is evaluated by simulations. Designed to be implemented in AMS (Autriamicrosystems) 0,35 μm CMOS process, the reference provides a stable voltage refer- ence equal to 1,354 V in the output working properly in the temperature range of -40 to 150oC. When EMI is injected, the circuit exhibits only 24,7 mV (when capacitive filters are included) of induced offset, for an interference signal varying in the frequency range of 150 kHz to 1 GHz / Mestre

Abstract The electrical pitting often occurs at the bearing of the ro-tating machinery due to the actions of the shaft voltage and the shaft current resulting in the arcing effect on the lubricated surface and causing the bearing failure. Since the mechanism of the electrical pitting cannot be microscopically observed in process, it is difficult to prevent the bearing damage. Hence, this study uses a static electrical pitting tester with sub -micrometer accuracy to experimentally investigate the effects of supply voltage, supply current, oil film thickness, and ad-ditive on the threshold condition of electrical pitting under the conventional bearing material pairs. Moreover, according to the SEM micrograph and EDS analysis, the mechanism of the pitted surfaces is investigated. According to the experimental results and the surface ob-servations of steel/steel pair using a paraffin base oil, three electrical pitting regimes are found under the influences of shaft voltage and oil film thickness, namely, pitting, transition, and no-pitting regimes. In the electrical pitting regime, the interface voltage, interface impedance, and interface power increases slightly with increasing oil film thickness at a certain supply current. However, the interface voltage and interface power increases with increasing supply current, and the inter-face impedance decreases with increasing supply current at a certain film thickness. Furthermore, the pitting area versus the interface power relationship is a cubic function. According to the experimental results and the surface ob-servations of babbitt alloy/steel pair using a paraffin base oil, two electrical pitting regimes are found under the influences of shaft voltage, oil film thickness, and melting point of material, namely, pitting and no-pitting regimes. The mechanism of electrical pitting on the babbitt alloy surface is significantly influenced by the interface power and the oil film thickness. At the smaller oil film thickness, the eroded surface of babbitt alloy exhibits a concave crater with a few micro-porosity in the vicinity of center region with a plateau on its surrounding, especially at high supply current. The polished track can be observed at the plateau. A large amount of tin element trans-fers to the steel ball surface because the molten tin contacts the ball. At the higher oil film thickness, only a little amount of metal element transfers to each other. The major pitting area of the babbitt alloy is caused at the initial stage of the arc dis-charge. With increasing arc discharge time, the pitting area increases slightly, and finally reaches a saturated value. According to the experimental results and the surface ob-servations of babbitt alloy/steel pair using an additive of MoS2 in a paraffin base oil, two electrical pitting regimes are found under the influences of shaft voltage, oil film thickness, and particle concentration of additive, namely, pitting and no-pitting regimes. The area of pitting regime increases with increasing additive concentration and supply current. Fur-thermore, the ratio of pitting area to the interface power in-creases with increasing additive concentration and supply current at the oil film thickness smaller than 6 mm. However, this ratio increases rapidly to about 10 times with increasing additive concentration and supply current as the oil film thickness increases from 6 mm to 10 mm. This results from the molten plateau that directly connects two specimens, and the interface power is mainly consumed at the heating of the pla-teau and the interfacial materials. According to the above re-sults, the growth model of the plateau on the pitting surface is proposed at the lubricated condition using an additive of MoS2 in paraffin base oil.

Thesis (M.S.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 27-28). Also available on the World Wide Web.

Thesis (doctoral)--Technische Universiteit Delft, 1997. / Includes bibliographical references.

Thesis (doctoral)--Technische Universiteit Delft, 1997. / Includes bibliographical references.

Made available in DSpace on 2014-06-11T19:22:31Z (GMT). No. of bitstreams: 0 Previous issue date: 2011-08-05Bitstream added on 2014-06-13T19:08:04Z : No. of bitstreams: 1 souza_fq_me_ilha.pdf: 803035 bytes, checksum: 9aab0ce0802cfc37e761960c21f93140 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Referências de tensão integradas com baixa sensibilidade à temperatura, tensão de a- limentação e eventos transitórios são componentes críticos na maioria dos circuitos integra- dos. Neste trabalho, além das restrições costumeiras, foi adicionada a preocupação com a in- terferência eletromagnética a qual vem ganhando muita importância devido a crescente polui- ção eletromagnética no ambiente. Assim, neste trabalho, propõe-se o projeto de uma referên- cia de tensão tipo bandgap com baixa susceptibilidade a interferência eletromagnética (EMI). O projeto deste circuito baseia-se na soma de duas correntes (referência de tensão baseada em corrente), uma com coeficiente complementar a temperatura absoluta (CTAT) e outra com coeficiente proporcional à temperatura absoluta (PTAT), aplicada sobre um resistor. Neste projeto, a susceptibilidade a interferência eletromagnética de uma referência de tensão band- gap é estudada por meio de simulação. Projetada para ser fabricada com a tecnologia CMOS 0,35 μm da AMS (Autriamicrosystems), a referência forneceu uma tensão de referência está- vel de 1,354 V em sua saída operando normalmente na faixa de temperatura de -40 a 150oC. Quando submetido à EMI, o circuito exibiu apenas 24,7 mV (quando filtros capacitivos são incluído) de offset induzido, para um sinal de interferência variando de 150 kHz a 1 GHz / Integrated voltage references with low sensitivity to temperature, supply voltage and transient events are critical requirements in the most of integrated circuits. In this work, be- sides the usual restrictions, was added to concern with electromagnetic interference which is gaining much importance due to increasing electromagnetic pollution on the environment. So, in this work, proposes the design of a bandgap voltage reference with low susceptibility to electromagnetic interference (EMI) is proposed. The design of the circuit is based on the sum of two currents (current-based voltage reference), one with coefficient complementary to ab- solute temperature (CTAT) and the other with coefficient proportional to absolute temperature (PTAT) into a resistor. In this work, the susceptibility to electromagnetic interference in a bandgap voltage reference is evaluated by simulations. Designed to be implemented in AMS (Autriamicrosystems) 0,35 μm CMOS process, the reference provides a stable voltage refer- ence equal to 1,354 V in the output working properly in the temperature range of -40 to 150oC. When EMI is injected, the circuit exhibits only 24,7 mV (when capacitive filters are included) of induced offset, for an interference signal varying in the frequency range of 150 kHz to 1 GHz

Power system harmonics are always an important issue in power networks as they can cause many negative impacts, such as equipment thermal stress, on installations within power networks. Recently, with the increasing connections of power electronic devices based Renewable Energy Source (RES) and High Voltage Direct Current (HVDC) transmission applications, harmonics in power networks, especially high frequency harmonics (>50th order or 2.5 kHz) are on the rise. Currently, the majority of conventional VTs, such as Wound-type Voltage Transformers (WVT) and Capacitor Voltage Transformers (CVT), are widely installed and used in High Voltage (HV) and Extra High Voltage (EHV) power networks for voltage measurement. Since most of them were mainly designed to measure voltage with the required accuracy at the fundamental frequency (i.e. 50Hz in the UK), they are limited to measuring high frequency harmonics due to the coupling of their internal inductive and capacitive elements. To achieve high frequency harmonic measurements, voltage measurement devices with wide frequency bandwidths are required. Recently, non-conventional VTs, such as optical voltage transducers, are commercially available, which could provide accurate voltage measurements over a wide range of frequency. However, before they can be considered by any power utilities, their frequency response performances must be tested at a rated fundamental voltage with required minimum harmonic injections from 100Hz to 5 kHz. This must require a test system which should be capable of providing a rated fundamental voltage up to 400kV with controllable harmonic injections at required levels from 100Hz to 5 kHz. Therefore, the objective of this project is to design and implement such a test system in the National Grid (NG) HV laboratory at the University of Manchester. However, the design and the implementation of such a test system bring many challenges; for instance, a lack of adequate equipment and considerable power to provide the required harmonic injections above 0.5% to the test object.In this thesis, an Instrument Voltage Transformer Frequency Response (VTFR) test system with three different voltage power source designs is presented; The voltage power source designs are: (i) Design 1 is based on a single power source inductive coupling method to provide both a rated fundamental voltage and controllable harmonics; (ii) Design 2 is based on two separate voltage power sources inductive coupling method to provide both a rated fundamental voltage and controllable harmonics; and (iii) Design 3 is based on two separate voltage power sources capacitive coupling method to provide both the rated fundamental voltage and controllable harmonics. A hybrid approach, which combines the VTFR test system with both the voltage power sources Design 2 and 3, is proposed for testing the frequency response of any type of VTs at their rated fundamental voltages with 1% harmonic injections from 100Hz to 5 kHz. The proposed VTFR test system with voltage power source designs were firstly validated at a relatively low voltage of 33kV in the HV laboratory. Then three different VTFR test systems were constructed based on available equipment for testing VTs from 11kV to 400kV. An 11kV, a 33kV WVT and a 400kV WVT and a 275kV CVT were tested. The test results were analyzed, compared and discussed. The models of the test systems were also established and simulated. Simulation results were analysed, compared and discussed.

No description available.

No description available.

The microprocessor faces a big challenge of heat dissipation. In order to enhance the performance of the microprocessor without increasing the heat dissipation, the leading microprocessor company, Intel, uses several methods to reduce the power consumption. Theses methods include enhanced sleep states control, the Speed Step technology, and multi-core architecture. These are closely related to the Voltage Regulator (VR), a dedicated power supply for the microprocessor and its control method. The speed of the VR control system should be high in order to meet the stringent load-line requirements with the high current and high di/dt, otherwise, a lot of decoupling capacitors are necessary. Capacitors make the VR cost and size higher. Therefore, the VR control method is very important. This dissertation discusses the way to increase the speed of VR without degrading other functions, such as the system efficiency, and the required control functions (AVP, current sharing and interleaving). The easiest way to increase the speed of the VR is to increase the switching frequency. However, higher switching frequency results in system efficiency degradation. This paper uses two approaches to deal with this issue. The first one is the architecture approach. The other is the fast transient control approach. For the architecture approach, a two-stage architecture is chosen. It is already shown that with a two-stage architecture, the switching frequency of the second stage can be increased, while keeping the same system efficiency. Therefore with the two-stage architecture, a high performance VR can be easily implemented. However, the light-load efficiency of two-stage architecture is not good because the bus voltage is designed for the full-load efficiency which is not optimized for the light load. The light-load efficiency is also important factor and it should be maximized because it is related to the battery life of mobile application or the energy utilization. Therefore, Adaptive Bus Voltage Positioning (ABVP) control has been proposed. By adaptively adjusting the bus voltage according to the load current, the system efficiency can be optimized for whole load range. The bus voltage rate of change is determined by the first stage bandwidth. In order to maintain regulation during a fast dynamic load, the first stage bandwidth should be high. However, it is observed from hardware when the first stage bandwidth is higher, the ABVP system can become unstable. To get a stable system, the first stage bandwidth is often designed to be slow which causes poor ABVP dynamic response. The large number of bus capacitors necessary for this also increases the size and cost. In this dissertation, in order to raise the first stage bandwidth, a stability analysis is performed. The instability loop (TABVP) is identified, and a small signal model to predict this loop is suggested. TABVP is related to the first stage bandwidth. With the higher first stage bandwidth, the peak magnitude of TABVP is larger. When the peak magnitude of TABVP touches 0dB, the system becomes unstable. Two solutions are proposed to reduce this TABVP magnitude without decreasing the first stage bandwidth. One method is to increase the feedforward gain and the other approach is to use a low pass filter. With these strategies, the ABVP system can be designed to be stable while pushing first stage bandwidth as high as possible. The ABVP-AVP system and its design are verified with hardware. For the fast transient control approach hysteretic control is chosen because of its fast transient and high light-load efficiency with DCM operation. However, in order to use the hysteretic control method for multiphase VR applications interleaving must be implemented. In this dissertation, a multiphase hysteretic control method is proposed which can achieve interleaving without losing its benefits. Using the phase locked loop (PLL), this control method locks the phase and frequency of the duty cycles to the reference clocks by modifying the size of the hysteretic band, to say, hysteretic band width. By phase shifting the reference clocks, interleaving can be achieved under steady state. During the load transient, the system loses the phase-locking function due to the slow hysteretic band width changing loop, and the system then reacts quickly to the load change without the interruption from the phase locking function (or the interleaving function). The proposed hysteretic control method consists of two loops, the fast hysteretic control loop and the slow hysteretic band width changing loop. These two nonlinear loops are difficult to model and analyze together. Therefore, assuming these two loops can be separated because of the speed difference, the phase plane model is used for the fast hysteretic control loop and the sampled data model is then used for the slow hysteretic band width changing loop. With these models, the proposed hysteretic control method can be analyzed and properly designed. However, if the transient occurs before the slow hysteretic band width changing loop settles down, the transient may start with the large hysteretic band width and the output voltage peak can exceed the specification. To prevent this, a hysteretic band width limiter is inserted. With the hardware, the proposed hysteretic control method and its design are verified. A two-phase VR with 300kHz switching frequency is built and the output capacitance required is only 860μF comparing to 1600μF output capacitance with the 50kHz bandwidth linear control method. That is about 46% capacitor reduction. The proposed hysteretic control method saturates the controller during the transient and the transient peak voltage is determined by the power stage parameters, the inductance and the output capacitors. By decreasing the inductance, the output capacitors are reduced. However, small inductance results in the low efficiency. In order to resolve this, the coupled inductor is used. With the coupled inductor, the transient inductance can be reduced with the same steady state inductance. Therefore, the transient speed can be faster without lowering down the system efficiency. The proposed hysteretic control method with the coupled inductor can be implemented using the DCR current sensing network. A two-phase VR with the proposed hysteretic control and the coupled inductor is built and the output capacitance is only 660μF comparing to 860μF output capacitance with the proposed hysteretic control only. A 23% capacitor reduction is achieved. And compared to the 50kHz bandwidth linear control method, a 60% capacitor reduction is achieved. / Ph. D.