The following dissertation addresses a novel low cost process developed to fabricate a Vertical Organic Field Effect Transistor (VOFET). The solution processable VOFET is designed, fabricated and tested in the context of bioengineering domains. The scope of distinct biomedical applications has also been explored. Organic thin-film transistors are gathering industrial attention as a potential candidate for future electronics analogous to silicon technology. Low fabrication cost, structural miniaturization and low operational voltage are the challenges for fabricating an Organic Field Effect Transistor (OFET). To create these devices, OFETs require new design paradigms and wet processing routes. However, conventional lateral OFET geometry cannot satisfy these demands because of process complexities and the high cost to achieve sub-micron channel length. Despite these barriers, solvent sensitivity towards organic semiconductors, electrode patterning and masking make this process more challenging than are associated with current technologies. Therefore, the need for production of a low cost high efficiency OFET is of high importance. The soluble organic semiconductor exhibits promising device properties. The growing demand of organic electronics poses great difficulty in adapting standard photolithography patterning for fabrication. The main issue is incompatibility in handling organic materials. To circumvent these challenges, a novel fabrication process has been developed to build OFETs in vertical geometry. The novelty of this process allows for creation of sub-micron channel devices at very low cost. Solution processed VOFET devices are fabricated using a 13,6-N-sulfinylacetamidopentacene (NSFAAP) precursor. Low cost fabrication techniques such as spin coating and drop casting are employed for achieving submicron channel length. Nanoscale devices, i.e. channel lengths, L=265nm, 300nm and 535nm, are respectively fabricated using the spin coating technique. Output characteristics are recorded at an operational voltage of 1volt. Short channel effects dominate the device performance, resulting in a linearity effect in I-V characteristics. Strategies, such as perforated source electrode design and drop casting techniques, are evolved and employed to minimize the short channel effects. Space Charge Limited Current (SCLC) effects, better known as short channel effects, are observed during I-V characterizations at high longitudinal fields. The drop casting technique is used over Patterned Electrode (PE) for reducing these SCLC effects. Thick channel devices, i.e. L=2µm, are fabricated to minimize the SCLC effects. Low cost polyimide 3M kapton tape is used as masking material in between the stacked layers. Time-temperature balance is optimized during the precursor to pentacene growth process. Metrological characterizations such as TEM, SEM, AFM, Raman Spectroscopy and X-RD are performed to confirm the precursor to pentacene conversion. AFM scanning illustrates dendritic pentacene molecular growth at 170°C annealing. Consequently, the conversion temperature is optimized around 200°C. In life sciences, there is always striving for translational technology development that can mimic, integrate and manipulate the biological system. Electrical signals enhance the capabilities of electronics to interact and understand the signaling pathways in a biological system. Keeping this in view, the potential applications into biomedical areas, such as flexible sensors and biomedical imagers, are proposed. VOFET has been proposed as a mainstay for flexible cardiac sensors and as imagers. OFET sensors could be designed to cover highly stretchy and arbitrary cardiac tissue. Sensor web integration with pacemakers and Implantable Cardioverter Defibrillator (ICD) device systems has been proposed. The OFET imaging sensor holds potential for early detection of cancer by detecting nuclear level changes in breast cancer images. Nuclear pleomorphic (shape and size distortion of cancerous nuclei) feature detection and analysis could be a step forward in the direction of digital pathology. The conventional analysis approach is time-consuming and error prone as it depends on visual inspection by pathologists. The proposed approach is parallel in nature and supports the existing method of cancer detection.

Avec l'évolution des technologies et le développement des objets connectés, la consommation des circuits est devenue un sujet important. Dans cette thèse nous nous concentrons sur la consommation des mémoires non volatiles à piégeage de charge. Afin de diminuer la consommation, différentes architectures ont vu le jour comme les mémoires 2T ou Split Gate. Nous proposons deux nouvelles architectures de mémoires permettant la diminution de la consommation par rapport à une mémoire Flash standard. La première, appelée ATW (Asymmetrical Tunnel Window), est composée d'une marche d'oxyde au niveau de son oxyde tunnel qui lui permet d'être moins consommatrice qu'une mémoire Flash standard. Une seconde architecture mémoire appelée eSTM (embedded Select Trench Memory) est aussi présentée. Son principal atout est la présence de son transistor de sélection qui est indispensable pour avoir une faible consommation. Grâce à son architecture, cette cellule est bien meilleure que l'architecture proposée précédemment (ATW). Une dernière étude a été réalisée afin d'optimiser le procédé de fabrication de la mémoire eSTM pour le rendre plus robuste. / With the evolution of technologies and the development of connected objects, the circuit consumption is becoming an important subject. In this thesis, we focus on the consumption of trap-charge non-volatile memories. To decrease the consumption, different architectures have emerged, like 2T or Split Gate memories. We propose two new memory architectures allowing to decrease the consumption compared to the standard Flash memory. The first, called ATW (Asymmetrical Tunnel Window), is composed of an oxide step in the tunnel oxide which allows to be less consumer than a standard Flash memory. A second memory architecture called eSTM (embedded Select Trench Memory) is also presented. Its main advantage is its select transistor which is essential to obtain a lower consumption. Thanks to its architecture, this cell is better than the previously proposed architecture (ATW). The last study has been performed to optimize the process flow of the eSTM memory to make it more robust.

Le but de cette thèse est de réaliser et d’étudier les propriétés électroniques d’un transistor à canal nanofil monocristallin à base de Si/SiGe (voir figure), élaboré par croissance CVD-VLS, à grille enrobante ou semi-enrobante en exploitant une filière technologique compatible CMOS. Ces transistors vont nous permettre d’augmenter la densité d’intégration et de réaliser de nouvelles fonctionnalités (par exemple : des interconnections reconfigurables) dans les zones froides d’un circuit intégré. La thèse proposée se déroulera dans le cadre d'une collaboration entre le laboratoire LTM-CNRS et le laboratoire SiNaPS du CEA/INAC/SP2M et utilisera la Plateforme Technologique Amont (PTA) au sein du pôle MINATEC. / The goal of this thesis is to build and characterize nanowire based field-effect-transistors. These FET will have either back or wrapping gate using standard CMOS process. Theses transistors will allow us to increase the integration density in back end stages of IC's fabrication and add new functionnalities suc as reconfigurable interconnections. The thesis will be done in collaboration between LTM/CNRS and CEA/INAC/SP2M/SiNaPS laboratories using the PTA facilities located in MINATEC.