<p>Electronic power devices made of silicon carbide promisesuperior performance over today's silicon devices due toinherent material properties. As a result of the material'swide band gap of 3.2eV, high thermal conductivity, itsmechanical and chemical stability and a high critical electricfield, 4H-silicon carbide devices have the potential to be usedat elevated temperatures and in harsh environments. Shortercarrier lifetimes and a reduction in the necessary width of thelow-doped drift zone in silicon carbide devices compared totheir silicon counterparts result in faster switching speedsand lower switching losses and thus in much more efficientpower devices.</p><p>High-voltage 4H-silicon carbide diodes have been fabricatedin a newly developed processing sequence, using standardsilicon process equipment. Epitaxial layers grown by chemicalvapor deposition (CVD) on commercial 4H-silicon carbidesubstrates were used as starting material for both mesa-etchedepitaxial and implanted p+n-n+ planar diodes, Schottky diodesand merged pn-Schottky (MPS) diodes, together with additionaltest structures. The device metallization was optimized to givea low contact resistivity on implanted and epitaxial layers anda sufficiently high Schottky barrier with a singlemetallization scheme. Different high-field termination designshave been tested and breakdown voltages of up to 4 kV onimplanted, field-ring terminated diodes were achieved,corresponding to 80% of the critical electric field. A 5kVepitaxial diode design with a forward voltage drop of 3.5V at acurrent density of 100Acm-2 equipped with an implanted junctiontermination extension (JTE) was also fabricated.</p><p>A new measurement setup was designed and built with thecapability of measuring current-voltage and capacitance-voltagecharacteristics of semiconductor devices at reverse biases upto 10kV. Together with these electrical measurements, theresults of other characterization techniques were used toidentify performance limiting defects in the fabricated siliconcarbide diodes. Increased forward voltage drop of bipolardevices during on-state operation was studied and it was shownthat the stacking faults causing forward degradation arevisible in scanning electron microscopy. With the help ofsynchrotron white-beam X-ray diffraction topographs (SWBXT),electron beam induced current (EBIC) and electroluminescencemeasurements of silicon carbide diodes, the role of screwdislocations as a dominant source of device failure in the formof localized microplasma breakdown was identified. Screwdislocations with and without open core have been found tocause a 20-80% reduction in the critical electric field of4H-silicon carbide diodes, both for low-voltage (150V) andhigh-voltage (~5kV) designs. While micropipes have almost beeneliminated from commercial silicon carbide material,closed-core screw dislocations are still abundant withdensities in the order of 10000cm-2 in state-of-the-art siliconcarbide epitaxial layers.</p>

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Thesis (M.S.)--West Virginia University, 2002. / Title from document title page. Document formatted into pages; contains vi, 87 p. : ill. (some col.). Vita. Includes abstract. Includes bibliographical references (p. 68-71).

Thesis (Ph.D.)--Tennessee Technological University, 2009. / Title from title page screen (viewed on Feb. 9, 2010). Includes bibliographical references.

Thesis (Ph. D.)--University of Missouri-Columbia, 2003. / Typescript. Vita. Includes bibliographical references (leaves 111-118). Also available on the Internet.

Thesis (Ph. D.)--University of Missouri-Columbia, 2003. / Typescript. Vita. Includes bibliographical references (leaves 111-118). Also available on the Internet.

Thesis--Auburn University, 2010. / Abstract. Includes bibliographic references (p.55-56).

The Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing performance and energy consumption of a processor since it allows for almost cubic reduction in dynamic power consumption with only a nearly linear reduction in performance. Due to its virtue, the DVS technique has been used for the two main purposes: energy-saving and temperature reduction. However, recently, a Dynamic Voltage Scaled (DVS) processor has lost its appeal as process technology advances due to the increasing Process, Voltage and Temperature (PVT) variations. In order to make a processor tolerant to the increasing uncertainties caused by such variations, processor designers have used more timing margins. Therefore, in a modern-day DVS processor, reducing voltage requires comparatively more performance degradation when compared to its predecessors. For this reason, this technique has a lot of room for improvement for the following facts. (a) From an energy-saving viewpoint, excessive margins to account for the worst-case operating conditions in a DVS processor can be exploited because they are rarely used during run-time. (b) From a temperature reduction point of view, accurate prediction of the optimal performance point in a DVS processor can increase its performance. In this dissertation, we propose four performance improvement ideas from two different uses of the DVS technique. In regard to the DVS technique for energy-saving, in this dissertation, we introduce three different types of margin reduction (or margin decision) techniques. First, we introduce a new indirect Critical Path Monitor (CPM) to make a conventional DVS processor adaptive to its given environment. Our CPM is composed of several Slope Generators, each of which generates similar voltage scaling slopes to those of potential critical paths under a process corner. Each CPR in the Slope Generator tracks the delays of potential critical paths with minimum difference at any condition in a certain voltage range. The CPRs in the same Slope Generator are connected to a multiplexer and one of them is selected according to a current voltage level. Calibration steps are done by using conventional speed-binning process with clock duty-cycle modulation. Second, we propose a new direct CPM that is based on a non-speculative pre-sampling technique. A processor that is based on this technique predicts timing errors in the actual critical paths and undertakes preventive steps in order to avoid the timing errors in the event that the timing margins fall below a critical level. Unlike direct CPM that uses circuit-level speculative operation, although the shadow latch can have timing error, the main Flip-Flop (FF) of our direct CPM never fails, guaranteeing always-correct operation of the processor. Our non-speculative CPM is more suitable for high-performance processor designs than the speculative CPM in that it does not require original design modification and has lower power overhead. Third, we introduce a novel method that determines the most accurate margin that is based on the conventional binning process. By reusing the hold-scan FFs in a processor, we reduce design complexity, minimize hardware overhead and increase error detecting accuracy. Running workloads on the processor with Stop-Go clock gating allows us to find which paths have timing errors during the speed binning steps at various, fixed temperature levels. From this timing error information, we can determine the different maximum frequencies for diverse operating conditions. This method has high degree of accuracy without having a large overhead. In regard to the DVS technique for temperature reduction, we introduce a run-time temperature monitoring scheme that predicts the optimal performance point in a DVS processor with high accuracy. In order to increase the accuracy of the optimal performance point prediction, this technique monitors the thermal stress of a processor during run-time and uses several Look-Up Tables (LUTs) for different process corners. The monitoring is performed while applying Stop-Go clock gating, and the average EN value is calculated at the end of the monitoring time. Prediction of the optimal performance point is made using the average EN value and one of the LUTs that corresponds to the process corner under which the processor was manufactured. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature within threshold temperature. / text

Owing to their inherent isolation and ability for remote interrogation, wireless sensors are an effective way to monitor the operation of high-voltage power transmission lines. A wireless sensor on a high-voltage line has the potential to form corona discharges, particularly on an exposed antenna. The effects of corona formation on the antenna of a wireless radio frequency (RF) communication system were studied. The physics of corona plasma formation and charge composition was analyzed, leading to a theoretical understanding of corona interaction with the antenna. Through a series of high-voltage experiments, the effects of corona on the impedance and gain of an antenna, as well as the RF interference generated by corona current pulses, were identified. RF interference and low-frequency corona current were observed to have the largest impact on a wireless RF system. Corona was found to have no significant impact on the impedance or gain of an antenna. Based on the results, design guidelines were proposed for an antenna and RF front end to be used in wireless high-voltage sensing applications.

Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time \((<0.1V/\mu s)\). This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities. / Engineering and Applied Sciences