For the future of sustainable energy, renewable energy will need to significantly penetrate existing utility grids. While various renewable energy sources are networked with high-voltage DC grids, integration between these high-voltage DC grids and the existing AC grids is a significant technical challenge. Among the limited choices available, the modular multi-level converter (MMC) is the most prominent interface converter used between the DC and AC grids. This subject has been widely pursued in recent years. One of the important design challenges when using an MMC is to reduce the capacitor size associated with each module. Currently, a rather large capacitor bank is required to store a certain amount of line-frequency related circulating energy. Several control strategies have been introduced to reduce the capacitor voltage ripples by injecting certain harmonic current. Most of these strategies were developed using trial and error and there is a lack of a systematic means to address this issue. Most recently, Yadong Lyu has proposed to control the modulation index in order to reduce capacitor ripples. The total elimination of the unwanted circulating power associated with both the fundamental line frequency and the second-order harmonic was demonstrated, and this resulted in a dramatic reduction in capacitor size. To gain a better understanding of the intricate operation of the MMC, this thesis proposes a state-space analysis technique in the present paper. Combining the power flow analysis with the state trajectory portrayed on a set of two-dimensional state plans, it clearly delineates the desired power transfer from the unwanted circulating energy, thus leading to an ultimate reduction in the circulation energy and therefore the required capacitor volume. / Master of Science

An auxiliary winding with an associated capacitor is added on the single-stage power factor corrector (PFC) based on fly-back conversion to reduce the ripple on the dc output voltage. The associated capacitor takes out partial energy at every switching cycle from the fly-back conversion and releases the stored energy to the load at the valley of the rectified line voltage. The negative effect of such an approach is that the converter does not draw a current from the AC line at the lower voltage near zero crossing, leading to deterioration in the power factor. This thesis analyzes how an auxiliary winding affects the voltage of the associated capacitor, which in turn changes the cut-in angle of the input current and thus the power factor of the AC source. To facilitate the implementation, the fly-back converter is operated at the boundary conduction mode (BCM). A design example is given for the 24 V, 48 W load, based on the derived equations. The laboratory circuit is built and tested to verify the computer simulations and analytical predictions. The experimental results confirm the circuit analyses on the converter performances.

This diploma thesis deals with elektrical power quality in DC grids. Electrical power is commodity and therefore it must be represented not just with quantitative, but also with qualitative parameters. Nowadays, there is an increasing demand for bigger implementation of renewable energy sources and more efficient power systems, which motivates installation of DC grids. However, development of DC grids is decelerated by lack of standardization alson in power quality. The work includes definition of power quality parameters and their measurement methodology.

This thesis proposes novel methods and comprehensive analysis for power loss calculation, DC-link current and voltage ripple estimation, and bus bar design in two-level three-phase voltage source inverters (VSIs). A novel method of MOSFET voltage rise- and fall-time estimations for the switching power loss calculation is developed. The estimation accuracy is significantly improved by the proposed method. In order to provide a reference for thermal management design, inverter power loss analysis is presented. Using the parameters obtained from the semiconductor device datasheets and inverter operating conditions, power loss calculations of three types of devices, namely IGBT, MOSFET, and diode, are discussed. The conduction power loss calculations for these three devices are straightforward; and, the switching power loss of IGBTs and diodes can be obtained from the energy losses given by datasheets. However, many MOSFET datasheets do not provide the switching energy losses directly. Therefore, to acquire MOSFET switching energy losses, switching transient times must be estimated as accurately as possible. The impacts of inverter anti-parallel diode reverse recovery on the DC-link current and voltage ripples are investigated. According to the analysis, the impact of diode reverse recovery on the voltage ripple is negligible, while the RMS value of current ripple is influenced by both diode reverse recovery and inverter switching frequency. A novel method is developed to calculate the ripple current RMS value and the estimation accuracy is significantly improved. Depending on the calculated current and voltage ripples, DC-link capacitor selection is introduced. Generally speaking, failures in the DC-link capacitors take place more frequently than the failures in other parts of the inverter system, and plenty of research has been focusing on minimizing the required DC-link capacitance. As a result, the accurate estimations of DC-link current and voltage ripples are vital in the optimization methods. In addition, with the accurate estimations, the over-design in the DC-link capacitance could be reduced. Finally, the design of a practical bus bar is presented. The DC current distribution is aff ected by the numbers and locations of the DC input tabs, while the AC current distribution is influenced by the numbers and locations of the installation holes for DC-link capacitors and semiconductor devices. Furthermore, parasitic parameters of the bus bar, especially the stray inductance and voltage spikes caused by this inductance during switching turn-o transients, are also discussed from the angle of the design rules and correlation between the parameters and bus bar geometry structure. In the end, a bus bar is designed with balanced current distribution and low stray inductance. / Thesis / Doctor of Philosophy (PhD)

The DC-side floating capacitors in the floating power modules of power converters are subject to high voltage fluctuation, due to the presence of reactive harmonic components. Utilizing passive capacitors, as done in traditional methods, helps reduce the DC-bus voltage ripple but makes the system bulky. An active capacitor can be integrated with the floating H-bridge power modules to remove the effect of the ripple powers on the DC bus. The auxiliary circuit, which is much smaller in size compared to an equivalent passive capacitor, helps increase the power density of the system. This work focuses on the analysis of power components, and the extension of the active capacitor to the Perturbation Injection Unit (PIU), in which the DC side is highly distorted by multiple harmonic components. A control scheme is proposed to compensate for these multiple harmonics and balance the DC-link voltage in the active capacitor. Also, an equivalent DC-bus impedance model is introduced, which is more accurate than that in existing works. Simulation studies and evaluation of the design have verified the effectiveness of the active capacitor solution. / Single-phase power converters have been widely used in many applications such as electric vehicles, photovoltaic (PV) systems, and grid integration. Due to their popular application, there is a need to reduce the sizes and volumes while still maintaining good performances of the systems. One of the most effective methods, which is a subject in many research works, is to replace the bulky passive capacitor bank in a system by an active capacitor. The active capacitor is designed to absorb the ripple components in the DC side of the converters, which results in a constant DC-link voltage. In comparison to the passive capacitor solution, the active capacitor is much smaller in size but can give a better DC-bus ripple performance. Therefore, the active capacitor has become an attractive solution for the single-phase converters. The active capacitor for the traditional rectifier, where the DC side is directly connected to a load, has been intensively investigated in the past decade. However, there is limited research regarding the active capacitor for rectifiers with floating H-bridge power modules. This work extends the application of the active capacitor to the Perturbation Injection Unit (PIU), which is a grid-connected single-phase rectifier with floating H-bridge power modules. The selection of a suitable active capacitor for the PIU is based on the evaluation of various active capacitor banks. Limits in existing control schemes, which prevent the extension of the active capacitor to the PIU, are thoroughly studied. An effective voltage-mode control scheme is then proposed for the selected active capacitor, which makes it an attractive solution for the PIU. Moreover, limits of the DC-bus impedance analysis using traditional assumptions in existing works are investigated, and an improved DC-bus impedance model is proposed. Based on the operation conditions of the PIU and the proposed impedance model, the active capacitor's components can be properly designed, and improved configurations in terms of the equivalent impedance can be analyzed. Simulation results, as well as the design and evaluation of the active capacitor, demonstrate great improvements in terms of volume and weight over the traditional passive capacitor bank.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.