Since 1970s, ever growing attention has been devoted by worldwide researchers and practitioners to the investigation of job release control. However, the need for control of flow of job/wafer into the wafer fabrication system is identified in the late 1988s. Subsequently, many release policies are developed and presented in the literature for improving its performance with respect to cycle time and throughput. Even though it is pointed out in the literature that there is a need for the development and analysis of policy that control the flow of job/wafer through the manufacturing process, still there is no exhaustive study in view of the previously developed release policies in the literature. Moreover, many new opportunities have evolved in the field of release policy in wafer fabrication industry due to the advancement in technology and computer science. It implies that near real-time decision making for efficient release policy is possible based on the global factory state. However, it appears from the literature that still to date the release policies, which are employed in real wafer fabrication system, are usually based on the static information. Release control/policy is emerging as an important research topic in the wafer fabrication industry given the extremely large capital investment and sales revenue of this industry. Release policy also hold practical significance for manufacturing managers, since neglecting it can lead to wide variations in shop workloads, can cause excessive backlogs, accomplishment of orders will be either too early or too late and there can be frequent need for expediting. All the challenges associated with the performance of the wafer fabrication system discussed here and the puzzle around the release policies and its impact on the wafer fabrication process, this research attempts to investigate existing release policies and proposing a few efficient release policies based on the knowledge gained from the existing release policies strength and weakness. Based on the insights gained from the existing release policies, three new closed loop release policies constant workload (CONSTWL), constant batch machine workload (CONSTBWL) and layer wise control (LWC) are developed by considering the parameters: workload in general, workload in batch machine, and re-entrant characteristics of the wafer fabrication system respectively. The conceptual significance in favour of these proposed closed loop release policies in improving performance of the wafer fabrication system is also outlined in this study. In the literature, few researchers clearly indicate that dispatching rule(s) influence the performance of wafer fabrication system either independently or in integration with release policies. Therefore, to empirically validate this fact, release policy is integrated with dispatching rule particularly applying on bottleneck (discrete processing machine) work station in this study. With these, the aims of proposed release policies are to efficiently improve the system performances in terms of average cycle time, standard deviation of cycle time and throughput. Accordingly, a simulation model is proposed and developed using Arena software for evaluating the performance of release policies in integration with dispatching rule applied on bottleneck work station in wafer fabrication environment. Further, to set the values of parameters in the simulation model, the cause and effect analysis is explored in this study by considering eight critical parameters or factors of the simulated wafer fabrication environment. It includes arrival rate, arrival distribution, processing time, maintenance schedule, operator’s schedule, batch size, dispatching rule and release policy. Simulation based cause and effect analysis not only helps in setting up the values of parameters in the proposed simulation model, but it also helps in strengthening the face validity of the developed simulation model. The verification and validation of the developed simulation model, which is a vital and fundamental aspect of simulation is discussed in detail in this study. Based on the analysis and the results observed from the cause and effect analysis, some modifications are incorporated and subsequently, the parameters values are set in the proposed simulation model for evaluating the performance of release policies integrating with dispatching rules. A series of simulation experiments are conducted using the proposed simulation model with systems conditions such as product mix, complexity of the process, level of machine unreliability, and system congestion level to study the relative effects of each of 18 release policies (one open loop release policy, 14 existing closed loop release policies, and 3 proposed release policies) in integration with dispatching rules (FIFO, LIFO and SRPT), considered in this study, at various throughput levels in the wafer fabrication environment. Particularly, the relative effect of integrating release policies and the dispatching rules are observed and analysed in terms of (a) the effect of dispatching rule on release policy, and (b) the effects of release policies on dispatching rules. It is observed from the overall inferences that dispatching rule: SRPT outperformed both FIFO and LIFO dispatching rule for all the considered release policies, except for the release policy: ‘TOTAL_CT’. Additionally, it is observed that for each of the eighteen release policies integrated with considered, the dispatching rule: SRPT produces less WIP inventory at the bottleneck work station for all throughput levels. The maximum deviation in delay (cycle time) is produced by dispatching rule: LIFO in all the release policies considered except for the release policy: ‘TOTAL_CT’ in which dispatching rule: SRPT produces maximum deviation in delay. Moreover, it is observed that the difference in mean delay with all three dispatching rules (FIFO, LIFO and SRPT) increases with the increase in throughput levels. Furthermore, it is observed that the throughput rate under all release policies (except ‘TOTAL_CT’) is more for dispatching rule: SRPT in comparison with both dispatching rules: FIFO and LIFO for nearly the same threshold values. The experimental results showed that proposed release policy: LWC reliably improves the system performance followed by the proposed release policy: CONSTWL and CONSTBWL with respect to both mean delay and standard deviation for corresponding throughput levels in wafer fabrication system. The characteristics of the proposed release policy: LWC are summarized and the same is presented as follows because this is proven to be best release policy among all the release policies considered in the proposed simulation model. The proposed release policy: LWC is a new measure of the work quantity on the shop floor system, which takes into account the location of jobs/wafers along the production line by employing re-entrant property of wafer fabrication system. As a result, it offers quick response to the stochastic events of the manufacturing system and can compensated the system disturbances in time. The proposed release policy: LWC offers more efficient control of flow of job/wafer in the wafer fabrication system with reduced delay (cycle time) and the standard deviation of delay (cycle time) for a given throughput level in comparison with almost all the release policies considered in this study in integration with all three dispatching rules considered and applied on bottleneck work station. For instance, from the analysis of simulation model, the proposed release policy: LWC reduces the average delay up to 98%, 95%, 90%, 89%, 49%, 35%, 21%, 17%, 13%, 12%, 10%, 9%, 9%, 9%, 6% and 4%, and reduces the standard deviation of delay up to 96%, 98%, 94%, 93%, 34%, 22%, 4%, 13%, 11%, 6%, 9%, 14%, 4%, 4%, 10% and 7% for a given throughput level, respectively in relation to other release polices: FRCP, EWIP, TOTAL_CT, PWR, EWC, DRCP, CONLOAD, WIPLCtrl, Droll, DEC, CONWIP, SA, RCONWIP, WR, CONSTBWL and CONSTWL respectively in integration with dispatching rule: SRPT. These improvements can also be understood from another aspect, that is, LWC can increase the system throughput rate for a given cycle time. The improvement is statistically significant according to the two sample t-test for all throughput values with a 95% confidence level. As the improvement of the proposed release policy: LWC is relatively less on the proposed release policies: CONSTWL and CONSTBWL with respect to mean delay, it can be inferred that the performance of CONSTWL and CONSTBWL is relatively better than other existing closed loop release policies for the scenarios considered in the simulation model. However, the best release policy: LWC provides satisfactory performance in comparison with other release policies for almost all scenarios considered in the simulation model. It is important to note that these proposed release policies can be easily applied in real wafer manufacturing systems because it possesses a simple logic and only the reference level need to be prescribed. The performance of four existing closed release policies that are FRCP, EWIP, TOTAL_CT and PWR are relatively worst in comparison with open loop release policy CONST. This is contradicting to the conclusions given in the literature by many authors that closed loop release policies are always better than open loop release policy with respect to cycle time and throughput measures. In fact, a reasonable closed loop release policy can provide better results than open loop release policy, if its objective and the release parameter are designed carefully, so that the release parameter can respond effectively to the dynamics of the manufacturing system. The reason for worst performance of these four existing closed loop release policies in comparison with open loop release policy and other existing policies is described in detail in this study. In order to see the impact of dispatching rules on a particular work station, batch machine work station, which usually has highest processing time in fabrication process, is considered in this study. The entire simulation experiments are replicated in the same manner except the basis that dispatching rules are applied on batch machine work station instead of bottleneck work station. Based on the analysis of the simulation results, the important observations are as follow: It is observed from the overall inferences that the influence of dispatching rules when applied to batch processing machine (diffusion) work station was not much on individual release policies, since the performance of all three dispatching rules provides nearly same performance at higher throughput level in the proposed simulation model. However, the performances of dispatching rule: SRPT in integration with all release policies considered in this study are summarized here because it produces less mean delay at most of the throughput values. In addition, from the analysis of simulation model, the proposed release policy: LWC reduces the average delay up to 97%, 93%, 87%, 85%, 22%, 17%, 15%, 15%, 13%, 11%, 10%, 10%, 9%, 6%, 6% and 2%, and reduces the standard deviation of delay up to 96%, 97%, 92%, 93%, 21%, 5%, 10%, 2%, 16%, 7%, 14%, 4%, 20%, 10%, 10% and 11% for a given throughput level, respectively in relation to FRCP, EWIP, PWR, TOTAL_CT, EWC, DEC, Droll, CONLOAD, SA, RCONWIP, WIPLCtrl, WR, DRCP, CONWIP, CONSTWL and CONSTBWL in integration with dispatching rule: SRPT, when applied on batch processing machine work station. The improvement is statistically significant according to the two sample t-test for most of the throughput values with a 95% confidence level. It is observed from overall inferences that the performance of all the release policies, considered in this study, in integration with dispatching rule: SRPT is better with respect to both mean delay and standard deviation of delay, when the dispatching rule is applied on the bottleneck (discrete machine, lithography) work station in the proposed simulation model. The performance of most of the release policies, considered in this study, in integration with dispatching rule: LIFO is better with respect to standard deviation of delay, when the dispatching rule is applied on the batch (batch machine, diffusion) work station. These results indicate that there is an influence of dispatching rule on the performance of wafer fabrication system if applied on batch machine work station or on bottleneck work station in integration with release policies. In addition, the effects of dispatching rules are highly dependent upon both the type of release policy used and the work station on which it is applied. Overall, the performance of the proposed release policies is proven to be very effective to system variability’s in scenarios considered in the simulation model. The significant impact of the choice of release policies on wafer manufacturing system performance is justified by the simulation experiments. It can be safely concluded that the efficient closed loop release policies that utilizes system information carefully based on the global factory state data can significantly improve the performance of wafer fabrication system. This thesis provides an extensive literature review covering several aspects of wafer fabrication process. Thereafter, a three new efficient closed loop release policies are developed and their workability are conceptually demonstrated with a framework and a flow diagram. The strength and the weakness of the existing release policies are conceptually highlighted and later it is proven to be true through comprehensive simulation study. A simulation model is developed by considering all the real-life fabrication environment for evaluating the performance of release policies in integration with dispatching rules. Cause and effect analysis is explored in proposed simulation model to set the parameters value. A series of simulation experiments are also constructed to empirically justify the conceptual significance of the proposed release policies.

PCM test structures are commonly used to check the produced wafers from the standpoint of the technologist. In general these structures are managed inside the FAB and are focused on standard device properties. Hence their development and analysis is not driven by analog circuit blocks, which are sensitive or often used. Especially for DFM/Y of analog circuits the correlation between design and technology has to be defined. The knowledge of electrical behavior of test structures helps to improve the designer's sensitivity to technological questions. This paper presents a method to bring the PCM methodology into the analog circuit design to improve design performance, yield estimation and technology correlation. We show how both analog circuit and PCM blocks can be simulated and analyzed in the design phase.

Planning and scheduling in semiconductor manufacturing is a difficult problem due to long cycle times, a large number of operational steps, diversified product types, and low-volume high-mix customer demand. This research addresses several problems that arise in the semiconductor industry related to front-end wafer fabrication operations and back-end assembly and test operations. The mathematical models built for these problems turn out to be large-scale mixed integer programs and hard to solve with exact methods. The major contribution of this research is to combine mathematical programming with metaheuristics to find high quality solutions within the time limits imposed by the industrial engineers who oversee the fabrication and test facilities. In order to reduce the size of problems that arise in practice, it is common to cluster similar product types into groups that reflect their underlying technology. The first part of the research is aimed at developing a greedy randomized adaptive search procedure (GRASP) coupled with path relinking (PR) to solve the capacitated clustering problem. The model is generic and can be applied in many different situations. The objective is to maximize a similarity measure within each cluster such that the sum of the weights associated with the product types does not exceed the cluster capacity in each case. In phase I, both a heaviest weight edge (HWE) algorithm and a constrained minimum cut (CMC) algorithm are used to select seeds for initializing the clusters. Feasible solutions are obtained with the help of a self-adjusting restricted candidate list. In phase II, three neighborhoods are defined and explored using the following strategies: cyclic neighborhood search, variable neighborhood descent, and randomized variable neighborhood descent (RVND). The best solutions found are stored in an elite pool. In a post-processing step, PR coupled with local search is applied to the pool members to cyclically generate paths between each pair. The elite pool is updated after each iteration and the procedure ends when no further improvement is possible. After grouping the product types into technologies, a new model is presented for production planning in a high volume fab that uses quarterly commitments to define daily target outputs. Rather than relying on due dates and priority rules to schedule lot starts and move work in process through the shop, the objective is to minimize the sum of the deviations between the target outputs and finished goods inventory. The model takes the form of a large-scale linear program that is intractable for planning horizons beyond a few days. Both Lagrangian relaxation and Benders decomposition were investigated but each proved ineffective. As a consequence, a methodology was developed which was more tailored to the problem’s structure. This involved creating weekly subproblems that were myopic but could be solved to optimality within a few minutes, and then postprocessing the results with a decomposition algorithm to fully utilize the excessive machine time. The heart of the post-processor consists of a rescheduling algorithm and a dispatching heuristic. The third part of the research focuses on the combinatorial problem of machinetooling setup and lot assignments for performing back-end operations. A new model and solution methodology are presented aimed at maximizing the weighted throughput of lots undergoing assembly and test, while ensuring that critical lots are given priority. The problem is formulated as a mixed-integer program and solved again with a GRASP that makes use of linear programming. In phase I of the GRASP, machine-tooling combinations are tentatively fixed and lot assignments are made iteratively to arrive at a feasible solution. This process is repeated many times. In phase II, a novel neighborhood search is performed on a subset of good solutions found in phase I. Using a linear programming-Monte Carlo simulation-based algorithm, new machine-tooling combinations are identified within the neighborhood of the solutions carried over, and improvements are sought by optimizing the corresponding lot assignments. / text

The manufacturing industries play a significant role in contributing to the economy of a country. Among various manufacturing industries, the semiconductor manufacturing (SM) industries is one of the fastest growing industries in the world having worldwide sales of $31 billion in the month of December 2016. Semiconductors are required by large number of industries, including Telecommunications, Medical Electronics, Automobile, Defence and Aerospace, Consumer Electronics, etc.,. Today, without semiconductors, the technology that we count on every day would not be possible. Because of these, the demand for SM industry is increased rapidly. In addition, most of the semiconductor based products‘ life is very short. Due to these, SM industry is highly competitive industry. Thus, to utilize the resources effectively, to handle the huge demand, and to deliver the product on-time, efficient scheduling is important in SM industry. SM process can be broadly classified into Wafer Fabrication (called as wafer fab), Wafer Probing, Assembly, and Final Testing. Scheduling is more important in wafer fab due to complex operations involving with multiple types of machines and re-entrant, expensive machines, and time-consuming process involved. Thus, this study concerns about scheduling in wafer fab, particularly diffusion operation. The diffusion operation, carried out on batch processing machine, heavily impacts the production rate of wafer fab and in turn the SM industry. This is due to the fact that, diffusion operation requires relatively longest processing time among all the operations in the wafer fab. Due to these, diffusion operation is the bottleneck operations in the wafer fab. Based on the detailed literature review, this study addresses a new research problem on dynamic scheduling (DS) of diffusion furnace(s) by considering together the various real-life problem characteristics: Non-identical parallel diffusion furnaces, Machine eligibility restriction, Incompatible-job families, Job and/or resource related real time events, and Non-agreeable release time and due-date. In addition, due to the importance of on-time delivery this study deals with five due-date based scheduling objectives: Total weighted tardiness (TWT), Number of tardy jobs (NT), On time delivery (OTD) rate, Total earliness and lateness (TE/L) and Maximum lateness (Lmax) as a single objective as well as multi objectives. Here, the multi objectives are developed, considering all the five due-date based scheduling objectives in a linear form by randomly assigning equal and unequal weights to each of the due-date based single objectives considered in this study. With these, the main objective of this thesis is to study the impact of job and/or resource related real time events (JR-RTE) on the relative efficiency of the proposed dynamic scheduling algorithms for diffusion furnace(s) while optimizing each of the due-date based scheduling objectives considered in this study. The research problem considered in this study is decomposed into five phases. From the analysis of the literature, it is observed that, there is no earlier study has the mathematical models for dynamic scheduling (DS) of diffusion furnaces to optimize all the due-date based scheduling objectives, considered in this study. Due to this, in the first phase, fourteen (0-1) mixed integer linear programming (MILP) models are proposed for DS of diffusion furnaces (seven models for DS of single diffusion furnace and seven models for DS of non-identical parallel diffusion furnaces) to optimize the due-date based single objectives: TWT, NT, OTD rate, TE/L, and Lmax and multi objectives: MO1 and MO2. All the proposed (0-1) MILP models are demonstrated for its workability by developing a suitable numerical example, LINGO set code (which generates each of the proposed (0-1) MILP model for any given data), and solving using LINGO solver. Further, based on the analysis of the literature a suitable experimental design is proposed and generated 15 small-scale test data. The computational complexity of each of the proposed (0-1) MILP models is discussed empirically by solving 15 small-scale test data. Due to the computational intractability of the proposed (0-1) MILP models for DS of diffusion furnaces, the second phase of the research focuses on a simple alternative approach based on dispatching rules, as the analysis of the literature reveals that dispatching rules are heavily used in the SM industry. However, there is no study in the literature presenting a comparative analysis of various dispatching rules particularly due-date based dispatching rules (DDR) for DS of diffusion furnace(s) to optimize various due-date based scheduling objectives. Accordingly, in the second phase, this study proposes a simple Greedy Algorithm (GA) based on DDR (called as GA-DDR) for Dynamic Scheduling of Single Diffusion Furnace (DS-SDF). Further, this study proposes twenty variants of GA-DDR considering various due-date based dispatching rules such as Earliest Due-Date, Flow Due-Date, Operational Due-Date, Modified Operational Due-Date, Critical Ratio, Minimum Slack First, Cost OVER Time, ten versions of Apparent Tardiness Cost (ATC) [including a new ATC rule proposed in this study] & five versions of Batch Apparent Tardiness Cost (BATC) [including a new BATC rule proposed in this study] for DS-SDF. All these twenty variants of GA-DDR are implemented in Turbo C. An experimental design is proposed in this phase for generating large-scale test data. Accordingly, 270 large-scale problem instances (representing 27 problem configurations and 10 instances per configurations) are generated. With these, a series of computational experiments are carried out to understand the relative efficiency of the twenty proposed variants of GA-DDR as follows: The efficiency of each of the twenty proposed variants of GA-DDR for DS-SDF with respect to each of the scheduling objectives considered in this study is analysed in comparison with optimal objective function value obtained from the corresponding (0-1) MILP models for 15 small-scale problem instances using the standard performance measures: Average Relative Percentage Deviation (ARPD) and Maximum Relative Percentage Deviation (MRPD). Further, for each of the 270 problem instances the efficiency of each of the twenty proposed variants of GA-DDR for DS-SDF with respect to each of the scheduling objectives is analysed in comparison with estimated objective function value, which is computed by giving the twenty feasible solutions obtained for each instances as input to Weibull distribution, (i) empirically using the performance measures: ARPD, MRPD, Integrated Rank (IRANK), & Global comparison based on Worst Solution (GCWS), and (ii) statistically by using the performance measures: Mean, Median, and 95% confidence interval. From the overall analysis, at the end of the second phase of the study, six efficient variants of GA-DDR among the twenty proposed variants of GA-DDR are identified for DS-SDF and discussed the insights for their better performance. In these six efficient variants of GA-DDR, two variants of GA-DDR uses the new ATC rule and/or BATC rule proposed by the author of this thesis. The second phase of the research considers only dynamic arrival of jobs in all the twenty variants of GA-DDR. But, in the real-life various unexpected job related real time events: rush job, due-date change, early/late arrival of job, change in job priority, and job cancellation and/or resource related real time events: machine breakdown, operator illness, tool failure, shortage of material, and defective material will occur in addition to the dynamic arrival of jobs. From the literature, it is observed that, all the studies in the dynamic scheduling of diffusion furnaces consider only future arrival of jobs and no study considering real time events. Further, to the best of our knowledge, the research studies on discrete processing machines develop various rescheduling algorithm or modify the existing algorithm whenever real time events occur while taking the scheduling decision. However, due to the longest operation time requirements at diffusion furnace and the computerized tracking system in the shop floor of wafer fab, we strongly propose a research hypothesis that modifying appropriately the work-in-process (WIP) data and/or the availability time of the corresponding diffusion furnace(s) for next scheduling depending upon the occurrence of job and/or resource related real time events respectively by utilizing the existing computerized tracking system in the shop floor is sufficient, and changing any proposed efficient algorithms for DS-SDF is not required. This hypothesis is proved both empirically and statistically in the third phase of this research, considering the twenty proposed variants of GA-DDR for DS-SDF and the proposed experimental design. Accordingly, this study propose a formal researchable hypothesis that there is no impact of JR-RTE on the relative efficiency of the twenty proposed variants of GA-DDR for DS-SDF while optimizing each of the due-date based scheduling objectives considered in this study. For testing the proposed hypothesis, this study proposed adjusted GA-DDR (with JR-RTE) for each of the proposed GA-DDR, in which there is step to update the WIP data if job related event occurs, and/or the next available time of corresponding diffusion furnace(s) for scheduling the same if resource related event occurs, before finalizing the scheduling decision. Each of the 270 large-scale problem instances generated using the proposed experimental design is solved by each of the 20 adjusted variants of GA-DDR (with JR-RTE). The comparison on the relative efficiency of each of the 20 proposed variants of GA-DDR and adjusted GA-DDR (with JR-RTE) is carried out using the performance measures: ARPD and MRPD [that is, ARPD(GA-DDR) vs. ARPD(adjusted GA-DDR with JR-RTE), and MRPD(GA-DDR) vs. MRPD(adjusted GA-DDR with JR-RTE)] while optimizing each of the seven scheduling objectives considered in this study. The empirical analysis of the comparisons reveals that there is no change in the relative efficiency of each of the 20 proposed variants of GA-DDR and the corresponding 20 adjusted variants of GA-DDR (with JR-RTE) while optimizing each of the scheduling objectives considered in this study. Further, this study proved the proposed hypothesis statistically by conducting the Spearman‘s rank order correlation between each of the 20 variants of GA-DDR and adjusted GA-DDR (with JR-RTE) for DS-SDF while optimizing each of the seven due-date based scheduling objectives considered in this study. From the empirical and statistical analyses carried out in the third phase of the study indicated that, no need to adjust the proposed variants of GA-DDR for any occurrences of real time events for obtaining efficient schedule. The SM industry normally would have more than one non-identical diffusion furnaces and that too in parallel. Due to some technical reasons, some jobs are processed only in specific diffusion furnace(s) available in the shop floor (this is called as machine eligibility restriction in scheduling theory). Hence, the impact of JR-RTE on the dynamic scheduling (DS) of non-identical parallel diffusion furnaces (NPDF) with machine eligibility restriction (MER) is addressed in the fourth phase of this study. In the fourth phase of the research study, the twenty proposed variants of GA-DDR for DS-SDF extended appropriately for DS-NPDF with MER [called as Extended GA-DDR (EGA-DDR)]. Further, a few new problem parameters required for NPDF with MER are identified from the literature and extended the proposed experimental design and generated 270 problem instances for representing NPDF with MER. For testing the proposed hypothesis on the impact of JR-RTE on DS-NPDF with MER, exactly the similar research processes carried out for comparing GA-DDR vs. adjusted GA-DDR (with JR-RTE) is followed for comparing EGA-DDR vs. adjusted EGA-DDR (with JR-RTE). Both empirical and statistical analyses clearly proved that there is no impact of JR-RTE on the relative efficiency of the twenty variants of EGA-DDR for DS-NPDF with MER while optimizing each of the due-date based scheduling objectives considered in this study and no need to adjust the variants of EGA-DDR for any occurrences of real time events for obtaining efficient schedule. So far, the study addressed the development of efficient GA-DDR and EGA-DDR for DS-SDF and DS-NPDF with MER respectively and studied the impact of JR-RTE on the relative efficiency of these proposed GA-DDR and EGA-DDR. Now, in the final phase of the research study, the impact of JR-RTE on the meta heuristics: Simulated Annealing (SA) and Tabu Search (TS), one at a time, for DS-SDF while minimizing TWT are studied. Accordingly, the required parameters for these two meta heuristics are identified from the literature and the meta heuristics: SA and TS, considering each of the six solutions obtained from the six efficient variants of GA-DDR respectively as initial solution are implemented. From the analysis of the solutions obtained, for each of the 270 problem instances, from each of the six efficient variants of GA-DDR and from each of the meta heuristics: SA and TS, it appears that the six efficient proposed variants of GA-DDR seems to be robust in terms of both quality and computational time requirements in obtaining efficient solution. Further, to study the impact of JR-RTE on meta heuristics: SA and TS, this study considers (a) six solutions obtained from each of the six efficient variants of GA-DDR for DS-SDF as the initial solution and obtained six final solutions respectively from each of the meta heuristics, and (b) six solutions obtained from each of the six adjusted variants of GA-DDR (with JR-RTE) for DS-SDF as the initial solution and obtained six final solutions respectively from each of the meta heuristics. For each of the meta heuristics, these two sets of final solutions, obtained for each of the 270 problem instances, are compared empirically and statistically, based on various performance measures considered in this study, and proved the research hypothesis defined in this study. The major research contributions of this study are as follows - By analyzing the literature on scheduling diffusion furnaces and the real-life situation in scheduling diffusion furnaces, a new research problem on dynamic scheduling (DS) of diffusion furnaces with incompatible-job families, machine eligibility restriction, non-agreeable release time and due-date, considering job and/or resource related real time events (JR-RTE) along with dynamic job arrival to optimize due-date based scheduling objectives: TWT, NT, OTD rate, TE/L, and Lmax as a single objective as well as multi objective was defined. - Seven (0-1) MILP models for each of DS-SDF and DS-NPDF were proposed for optimizing each of the seven due-date based scheduling objectives considered in this study and the computational complexity was observed. - Due to the computational complexity of the proposed (0-1) MILP models and the popularity of the dispatching rules in the semiconductor manufacturing industry, this study proposed and compared the twenty variants of (i) greedy algorithm based on due-date based dispatching rules (GA-DDR) for DS-SDF, and (ii) Extended GA-DDR for DS-NPDF with machine eligibility restriction (MER). - The impact of JR-RTE on the twenty proposed variants of (a) GA-DDR for DS-SDF, and (b) EGA-DDR for DS-NPDF with MER was studied and observed that modifying the data appropriately by utilizing the existing computerized tracking system available in the shop floor is sufficient and rescheduling or modifying the existing algorithms are not required when the occurrences of JR-RTE happens. - Finally, single solution based meta heuristics: Simulated Annealing (SA) and Tabu Search (TS), considering each of the six solution obtained from each of the six efficient variants of GA-DDR proposed in this study as initial solution respectively, were proposed for DS-SDF to minimize TWT. Performance analysis of the solution obtained from each of the six efficient variants of GA-DDR and from each of the meta heuristics were carried out and observed that efficient variants of GA-DDR seems to be robust in terms of both quality and computational time requirements in obtaining efficient solution. In addition, the impact of JR-RTE on the meta heuristics: SA and TS were studied and proved the research hypothesis proposed in this study. Although, this study considers many real-life problem characteristics, there are certain limitations in this study. Though this study proposed mathematical model for DS-NPDF, the required additional constraint on Machine Eligibility is not considered in this study. Further, the impact of JR-RTE on the meta heuristics: SA and TS were studied considering only DS-SDF and not for DS-NPDF with MER. In addition to overcoming the limitations mentioned here, there are many immediate future research directions for the problem studied in this thesis such as proposing the greedy algorithms for scheduling diffusion operation along with upstream or downstream operation, and proposing population based meta heuristics for the research problem defined in this study.

晶圓製程設備商必須充分利用全球化智慧資源規劃，發展企業策略，才能創造企業競爭力和成長動能。經過多次的景氣循環，晶圓設備產業已經成為少數廠商全球激烈競爭的環境，特別是仍有兩家設備供應商以上的產品線。對於客戶而言，購買設備的主要因素來自於廠商製程能力和成本的優勢。除了少數關鍵製程由一家壟斷外，客戶都可以在每一個新製程世代(Technology node)找到兩家廠商評估設備和技術需求。在贏者全拿的壓力與吸引力下，在每一個新製程世代的銷售週期中，晶圓設備商都必須要充分利用智慧資本化的效益，掌握客戶的技術、量產時程，才能確保銷售空間。在發展策略上，為面對高技術競爭但是低成長的產業環境，晶圓設備商必須要透過併購和整合其核心技術相關新事業才能同時整合既有智慧資源和創造成長。 不管從市場規模和產業鏈來看，台灣的半導體產業已經成為全球最重要的製造據點，也是台灣最重要的產業之一。半導體製造廠龐大的資本支出和相關需求更讓台灣成為各半導體設備商的銷售服務的兵家必爭之地。根據SEMI的最新市場調查，總計台灣2007年的半導體設備市場達到106.5億美元，較2006年大幅成長45.2%，正式超越日本成為全球最大半導體設備投資市場。在產業鏈中，晶圓製程設備除了是晶圓廠最大資本支出外，還是產業技術發展的供應者。很可惜的是，雖然擁有龐大的商機做後盾，台灣卻沒有及時發展這個領域。在轉換成本、專利、和領導晶圓製造商合作開發和人才、資金等高產業門檻下，除了自動化設備較有進展外，台灣在晶圓製程設備產業的自給率普遍低於5%，技術、智財和人才還是掌握在外國的晶圓製程設備廠商。在沒有整合產、官、學、研等資源和適合的智財管理規劃下，在需要高度基礎科學和長遠技術發展的晶圓製程設備產業，我們設備自制化的結果不高，並不令人訝異。晶圓製造業者的議價和技術自主能力因此而受到拘束，所發展的智財也沒有太大價值和效用。 本研究目的希望以智慧資源規劃為研究方法，進行晶圓製程設備產業的實證研究。先就市場特性分析晶圓製程設備產業概況，接著探討廠商如何運用智慧資源規劃的資本化和產業結構化切入市場，最後在實證研究上以分析主要晶圓製程設備廠商的專利能量和最新奈米技術High-k/Metal Metal Gate探討產業的技術發展趨勢與廠商智慧資源規劃的運用和佈署。期望從綜合上述論點，做為台灣是否適合發展晶圓製程設備和又該如何準備智慧資源規劃的參考。 / Global intellectual resource planning (IRP) is cruicial in industrial strategy for wafer fabrication equipment vendors to develop competence and growth momentums. After several business cycles during the past few decades, this industry has become a very competitive market of a few players. For their customers, the key decision factors are the technology capability and cost of the vendors. Except for some critical process equipments dominated by only one vendor, the customers can identify 2 vendors to evaluate their equipment and cost performance. That Winner takes all become the pressure and attraction of the industry. The vendors must fully apply the value of intellectual property and overhaul their customer’s technology and production roadmap to ensure their share in the market. To cope with the market challenges of low growth and highly competitiveness, the vendors must incoporate and integrate other new companies of their core technology to consolidate given intellectual resource and create better achievements. Either from the perspective of market size and industry value chain, Taiwan has played the most important role in semiconductor manufacturing industry worldwide. To extend their market share and keep in the lead, the foundry and DRAM companies have aggressively invested in the production of 300mm fabs. The vast investments and its production demands have made Taiwan the most competitive place in semiconductor equipment markets. According to the SEMI most update, the business volume of Taiwan semiconductor equipments market reached to US$10.65 billion in 2007, with an impressive growth of 45.2% more than 2006. Taiwan has overtaken Japan and become the largest semiconductor equipment markets in the world. In the industry value chain, the wafer fabrication equipments not only accounted for the greatest capital expenditure of fibs but also the foundation for the process technology development. It is a pity that the equipments industry in Taiwan did not flourish as along with the great market here. All the key technologies, people, materials and components are manipulated by foreign vendors. This situation resulted in an un-balanced development in domestic semiconductor industry as well as the bargain power and self-owned technology. The related developed intellectual rights can not show the real value and effect. With the high entry barriers of transfer cost, patents, professionals and investments of wafer fabrication equipments markets, Taiwan vendors take less than 5% in the market share, except for some progress in automation equipments of lower IP, capital and transfer cost barriers. The Taiwan vendors have not demonstrated capability in process technology to penetrate the markets. The wafer fabrication equipment market growth was a result of o the outsource investment from Europe, US and Japan fabs. It turns out that the technology, IP and people are still possessed by foreign vendors. Without the synergy and integration of government, academia and industry and intangible resource planning, it is not surprising that our production localization ratio is relatively low. Thus, the thesis will elaborate the case study in the way of intellectual resource planning. First, the research will analyze the industrial characteristics of wafer fabrication equipment market. In the followings, this research will discuss how vendors can apply IRP to penetrate the market. Finally, this research will analyze the patents of major vendors and High-k/Metal Gate process technology to elaborate the industry technology cycles and new technology development strategy. As a result, the thesis will try to discuss if it is suitable for Taiwan to develop the wafer fabrication equipment market and also serve for reference how to prepare the intellectual resource planning.

本論文採用實地實證研究，以一家專業晶圓代工廠商為研究對象，詳細分析在晶圓代工的製造環境下，產品多樣性及製造彈性對生產品質、生產週期時間、設備生產力與生產成本之影響。不同於過去研究，以外部彈性(例如：產品組合彈性、新產品彈性等)為研究重心，本論文以內部彈性為研究範疇，涵蓋機器彈性與路徑彈性兩種彈性型態，據以彌補現存製造彈性文獻的缺口。 關於產品多樣性與製造彈性對生產績效與生產成本之直接影響，本論文首先以等候理論與整數規劃模型為基礎，加入實地環境特性的考量，推導研究假說與實證模型；繼而，蒐集來自個案公司6個月的詳細生產資料，包括兩類資料型態：機台水準(machine-level)與生產批量水準(lot-level)進行實證分析。綜合理論模型與實證分析結果，本論文發現：在晶圓代工的製造環境中，由於製程高度自動化之故，產品多樣性對生產績效的直接影響並不顯著，但因研發與工程實驗所產生的環境變異性則對生產績效具有顯著的負面影響；在製造彈性方面，吾人則發現路徑彈性不僅有助於生產週期時間的縮短，也對品質與成本績效具有顯著的正向影響，而機器彈性雖有助於設備生產力的提昇與生產成本的降低，但對生產品質則有顯著的負面影響，此外，本研究也發現：製造彈性與設備生產力、生產週期時間及生產成本之間存在非線性關係，並呈現報酬遞減的趨勢，隱含：極大化製造彈性並非最佳，有限的彈性水準即可達到最大的彈性利益。 考慮製造彈性的價值高低與環境不確定性密切相關，本研究進一步採用路徑分析檢視產品多樣性、製造彈性、環境不確定性與生產績效之間的關聯性，基於本研究以內部彈性為研究範疇，並以製造環境為研究客體，依據生產管理文獻，由製程時間變異性、到達時間變異性及產品需求變異性三項指標定義製造環境的不確定性。實證結果顯示：產品多樣性主要係透過環境不確定性間接影響生產績效，而機器彈性與路徑彈性則有助於調和內部不確定性對生產績效的負面影響，進而達成生產績效的提昇。本論文之分析結果隱含：過去管理會計研究認為產品多樣性對生產績效的影響主要來自於批量作業活動(batch-level activities)與產品支援活動(product-sustaining activities)的增加，而忽略產品多樣性對環境不確定性的影響，可能低估產品多樣性的攸關成本，尤其在一高利用率與高度動態的生產環境中，產品多樣性透過環境不確定性對生產績效的間接影響可能大於產品多樣性對生產績效的直接影響；另一方面，本研究指出：在一動態環境中，廠商可透過製造彈性的提昇，降低環境不確定性對生產績效的負面影響，但最適彈性水準的決定則須取決於製造彈性與其他生產績效衡量之間的函數關係。 / This thesis reports the results of a field empirical study examining the impact of product variety and manufacturing flexibility on production quality, cycle time, equipment productivity, and production cost within the context of semiconductor wafer fabrication facilities. To fill the gap in existing research, I attempt to study internal flexibility, rather than external flexibility (e.g., product flexibility, mix flexibility). Two types of internal flexibility are selected, which are machine flexibility and routing flexibility. Using both machine-level and lot-level production data from one dedicated wafer fabrication plant, this thesis examines the direct impact of product variety and manufacturing flexibility on production performance and production cost. Empirical results suggest that greater product variety does not have a significant impact on equipment productivity but does have a significant adverse impact on production quality. Moreover, I find support for the hypotheses that greater routing flexibility has a significant positive impact on quality, time, and cost performance. As for machine flexibility, it has a significant positive impact on equipment productivity and cost performance, but has a significant negative impact on production quality. Furthermore, I also find a non-linear relation between manufacturing flexibility and equipment productivity, cycle time, and production cost. This implies that maximizing the level of manufacturing flexibility is not necessarily optimal for firms. Limiting the flexibility level may actually have the greatest benefit. To further clarify the mechanisms through which variety and flexibility impacts performance, I move beyond the direct effects and investigate the linkage between product variety, manufacturing flexibility, environmental uncertainty and production performance. Based on the operations research, environmental uncertainty is operationally defined as the process time variation, inter-arrival time variation, and output variation. Results from path analysis indicate that product variety negatively affects production performance through environmental uncertainty. This finding stands in direct contrast to the general belief in management accounting research that greater product variety leads to an increase in the number of batch-level activities and product-sustaining activities, which thus increase the production cost. In other words, the reported cost of product variety may be underestimated, because we do not consider the impact of product variety on environmental uncertainty. The magnitude of the underestimation is especially greater in a highly congested and stochastic environment. Empirical results also show that machine flexibility and routing flexibility mitigate the adverse impact of environmental uncertainty on production performance.

PCM test structures are commonly used to check the produced wafers from the standpoint of the technologist. In general these structures are managed inside the FAB and are focused on standard device properties. Hence their development and analysis is not driven by analog circuit blocks, which are sensitive or often used. Especially for DFM/Y of analog circuits the correlation between design and technology has to be defined. The knowledge of electrical behavior of test structures helps to improve the designer's sensitivity to technological questions. This paper presents a method to bring the PCM methodology into the analog circuit design to improve design performance, yield estimation and technology correlation. We show how both analog circuit and PCM blocks can be simulated and analyzed in the design phase.