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Generation of dicing damage in passivated silion wafersRepole, Kenzo K. D 12 1900 (has links)
No description available.
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Generation of dicing damage in silicon wafersEbbutt, Ralph 08 1900 (has links)
No description available.
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Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integrationBakir, Muhannad S. 01 December 2003 (has links)
No description available.
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Compliant Wafer Level Package (CWLP)Patel, Chirag Suryakant 05 1900 (has links)
No description available.
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Growth of Mono-Oriented Superconducting Hexagonal MoN on Amorphous SubstratesAlsaadi, Rajeh S. 19 April 2022 (has links)
Hexagonal molybdenum nitride (δ-MoN) is one of the hardest superconductors, and its superconducting properties depend on the crystalline structure and the substrate of use. Herein, a versatile growth method has been utilized to grow single-crystalline (SC) δ-MoN thin films on any arbitrary substrate of interest. SC δ-MoN films have been achieved on amorphous substrates via the transfer of MoS2 precursors followed by chemical phase conversion. The transferred SC δ-MoN film on an amorphous SiO2/Si substrate exhibits superconductivity at Tc = 4.75 with an upper critical field Hc2(0) = 8.24 K. The effect of the transfer process was assessed by directly growing SC δ-MoN on an Al2O3 substrate, which showed enhanced superconductivity properties due to the nonuniformity in film thickness that the transfer process induces. The crystalline structure effect on superconductivity was studied by directly growing amorphous δ-MoN film on an amorphous SiO2/Si substrate. The amorphous film showed degraded superconducting behavior and confirmed that disorders in the crystal structure suppress superconductivity. The upper critical fields of the non-transferred δ-MoN films exceeded their Pauli paramagnetic limits, which could give rise to the existence of the Ising pairing effect, but further studies are needed to confirm this behavior.
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Investigation of Copper Out-Plating Mechanism on Silicon Wafer SurfaceChien, Hsu-Yueh 08 1900 (has links)
As the miniaturization keeps decreasing in semiconductor device fabrication, metal contamination on silicon surfaces becomes critical. An investigation of the fundamental mechanism of metal contamination process on silicon surface is therefore important. Kinetics and thermodynamics of the copper out-plating process on silicon surfaces in diluted HF solutions are both evaluated by several analytical methods.
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Modellierung eines wafer-scale Systems für pulsgekoppelte neuronale NetzeScholze, Stefan, Ehrlich, Matthias, Schüffny, Rene´ 08 June 2007 (has links) (PDF)
Beim Aufbau von konfigurierbaren wafer-scale Systemen für pulsgekoppelte neuronale Netze werden hohe Anforderungen an die Kommunikation
zwischen einzelnen Komponenten gestellt. Zur Unterstützung des Hardwareentwurfs, aber auch um die parallele Entwicklung der Software zu ermöglichen,
können Simulationsmodelle verwendet werden. Der Aufbau der Architektur und die Implementierung als SystemC-Modell werden beschrieben.
Aus der Simulation sind Rückschlüsse auf die Architektur möglich, es ergeben sich aber auch Anforderungen an die zu entwickelnde Softwareumgebung.
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Wafer-level encapsulated high-performance mems tunable passives and bandpass filtersRais-Zadeh, Mina. January 2008 (has links)
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Farrokh Ayazi; Committee Member: James D. Meindl; Committee Member: Joy Laskar; Committee Member: Mark G. Allen; Committee Member: Paul A. Kohl. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Wafer-scale growth method of single-crystalline 2D MoS2 film for high-performance optoelectronicsXu, Xiangming 26 October 2020 (has links)
2D semiconductors are one of the most promising materials for next-generation electronics. Realizing continuous 2D monolayer semiconductors with single-crystalline structure at the wafer scale is still a challenge. We developed an epitaxial phase conversion (EPC) process to meet these requirements. The EPC process is a two-step process, where the sulfurization process was carried out on pre-deposited Mo-containing films. Traditionally, two-step processes for 2D MoS2 and other chalcogenides have suffered low-quality film and non-discontinuity at monolayer thickness. The reason was regarded as the low lattice quality of precursor film. The EPC process solves these problems by carefully preparing the precursor film and carefully controlling the sulfurization process. The precursor film in the EPC process is epitaxial MoO2 grown on 2″ diameter sapphire substrate by pulsed laser deposition. This epitaxial precursor contains significantly fewer defects compared to amorphous precursor films. Thus fewer defects are inherited by the EPC MoS2 film. Therefore, EPC MoS2 film quality is much better. The EPC prepared monolayer MoS2 devices to show field-effect mobility between 10 ~ 30 cm2·V-1s-1, which is the best among the two-step process. We also developed a CLAP method further to reduce the defects in the precursor oxide film; thus, in-plane texture in the thicker MoS2 film was eliminated, and a single-crystalline structure was obtained in the wafer-scale MoS2 films. The potentially feasible technique to further improve the 2D film quality is pointed out for our next research plan. Meanwhile, the epitaxial phase conversion process was proposed to be as a universal growth method. Last but not least, we demonstrate several potential applications of the wafer-scale single-crystalline MoS2 film we developed, such as logic circuits, flexible electronics, and seeding layer of van der Waal or remote epitaxial growth.
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A Materials Approach to Silicon Wafer Level Contamination Issues from the Wet Clean ProcessHall, Lindsey H. (Lindsey Harrison) 12 1900 (has links)
Semiconductor devices are built using hyperpure silicon and very controlled levels of doping to create desired electrical properties. Contamination can alter these precisely controlled electrical properties that can render the device non-functional or unreliable. It is desirable to determine what impurities impact the device and control them. This study consists of four parts: a) determination of acceptable SCI (Standard Clean 1) bath contamination levels using VPD-DSE-GFAAS (Vapor Phase Decomposition Droplet Surface Etching Graphite Furnace Atomic Absorption Spectroscopy), b) copper deposition from various aqueous HF solutions, c) anion contamination from fluoropolymers used in chemical handling and d) metallic contamination from fluoropolymers and polyethylene used in chemical handling. A technique was developed for the determination of metals on a silicon wafer source at low levels. These levels were then correlated to contamination levels in a SCI bath. This correlation permits the determination of maximum permissible solution contaminant levels. Copper contamination is a concern for depositing on the wafer surface from hydrofluoric acid solutions. The relationship between copper concentration on the wafer surface and hydrofluoric acid concentration was determined. An inverse relationship exists and was explained by differences in diffusion rates between the differing copper species existing in aqueous hydrofluoric acid solutions. Finally, sources of contamination from materials used in chemical handling was studied. The predominant anion contamination from fluoropolymers was found to be fluorides. Metallic contamination from fluoropolymers and polyethylene was also studied. The primary metal contamination comes from the actual fabrication of the polymer and not from the polymer resin.
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