To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for flexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

A tablet computer antenna array for WWAN/LTE and LTE MIMO operations is proposed. The antenna array comprises a main antenna and an auxiliary antenna. The main antenna is an eight-band coupled-fed antenna, which can cover the GSM850/900/1800/1900/UMTS and LTE700/2300/2700 operations. The auxiliary antenna is a three-band antenna, which can cover the LTE700/2300/2500 operation and occupies a small size. Acceptable isolation between the main and auxiliary antennas has also been obtained, which makes it promising for the main and auxiliary antennas to perform LTE MIMO operation in the LTE700/2300/2500 bands. Effects of the internal tablet computer antenna on the user¡¦s body are also studied. The obtained results show that the antenna can meet the 1-g body SAR specification of less than 1.6 W/kg by selecting a proper distance between the antenna and the flat phantom. Also, since the user¡¦s body is a lossy material, a decrease in the antenna¡¦s radiation efficiency is observed when the user¡¦s body is in the vicinity of the internal antenna.

In this thesis, WWAN/LTE and LTE MIMO antennas for ultrabook computers are presented. The MIMO antenna system comprises an eight-band LTE/WWAN antenna and a three-band LTE antenna. The bandwidth of the eight-band LTE/WWAN antenna is enhanced by using an embedded parallel resonant circuit, which can result in dual-resonance excitation of the lowest resonant mode of the antenna. The bandwidth of the antenna¡¦s lower band can hence cover the LTE700/GSM850/900 operation. A design technique of improving the isolation of the MIMO antenna system is also presented. The isolation enhancement is obtained by embedding a 0.5-wavelength slot in the conductive supporting plate of the upper cover of the ultrabook computer. The embedded slot can attract the excited surface currents in the conductive supporting plate and decrease the coupling between the MIMO antennas through the coupling of the surface currents. The isolation between the MIMO antennas can hence be enhanced. Moreover, this technique will not lead to decreased radiation efficiency and impedance matching of the MIMO antennas, which is attractive for practical applications.

The research topics presented in this dissertation focus on validation of customer-level voltage synchrophasor data for transmission system analysis, detection and categorization of power system events as measured by phasor measurement units (PMUs), and identification of the influence of power system conditions (wind power, daily and seasonal load variation) on low-frequency oscillations. Synchrophasor data can provide information across entire power systems but obtaining the data, handling the large dataset and developing tools to extract useful information from it is a challenge. To overcome the challenge of obtaining data, an independent synchrophasor network was created by taking synchrophasor measurements at customer-level voltage. The first objective is to determine if synchrophasor data taken at customer-level voltage is an accurate representation of power system behavior. The validation process was started by installing a transmission level (69 kV) PMU. The customer-level voltage measurements were validated by comparison of long term trends and low-frequency oscillations estimates. The techniques best suited for synchrophasor data analysis were identified after a detailed study and comparison. The same techniques were also applied to detect power system events resulting in the creation of novel categories for numerous events based on shared characteristics. The numerical characteristics for each category and the ranges of each numerical characteristic for each event category are identified. The final objective is to identify trends in power system behavior related to wind power and daily and seasonal variations by utilizing signal processing and statistical techniques. / text

Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 59-63). Also available in electronic format on the Internet.

Recent years have seen the significance of utilizing time-synchronized, high resolution measurements from phasor measurement units (PMUs) to develop and implement wide-area monitoring, protection and control (WAMPAC) systems. WAMPAC systems aim to provide holistic view of the power system and enable detection and control of certain power system phenomena to enhance reliability and integrity of the grid. This thesis focuses on the design, development and experimental validation of WAMPAC applications, and investigates their vulnerability to time synchronization impairment. To this purpose, a state-of-the-art real-time hardware-in-the-loop (RT-HIL) test-bench was established for prototyping of synchrophasor-based applications. This platform was extensively used throughout the thesis for end-to-end testing of the proposed WAMPAC applications. To facilitate the development of WAMPAC applications, an open-source real-time data mediator is presented that parses the incoming synchrophasor stream and provides access to raw data in LabVIEW environment. Within the domain of wide-area protection applications, the thesis proposes hybrid synchrophasor and IEC 61850-8-1 GOOSE-based islanding detection and automatic synchronization schemes. These applications utilize synchrophasor measurements to assess the state of the power system and initiate protection / corrective action using GOOSE messages. The associated communication latencies incurred due to the utilization of synchrophasors and GOOSE messages are also determined. It is shown that such applications can have a seamless and cost-effective deployment in the field.   Within the context of wide-area control applications, this thesis explores the possibility of utilizing synchrophasor-based damping signals in a commercial excitation control system (ECS). For this purpose, a hardware prototype of wide-area damping controller (WADC) is presented together with its interface with ECS. The WADC allows real-time monitoring and remote parameter tuning that could potentially facilitate system operators’ to exploit existing damping assets (e.g. conventional generators) when changes in operating conditions or network topology emerges. Finally the thesis experimentally investigates the impact of time synchronization impairment on WAMPAC applications by designing RT-HIL experiments for time synchronization signal loss and time synchronization spoofing. It is experimentally demonstrated that GPS-based time synchronization impairment results in corrupt phase angle computations by PMUs, and the impact this has on associated WAMPAC application. / <p>QC 20171121</p> / smart transmission grid operation and control (STRONg2rid)

Recent major electrical disturbances highlight the extent to which modern societies depend on a reliable power infrastructure and the impact of these undesirable events on the economy and society. Numerous blackout models have been developed in the last decades that capture effectively the cascade mechanism leading to a partial or complete blackout. These models usually consider only the state of the electrical part of the system and investigate how failures or limitations in this system affect the probability and severity of a blackout.However, an analysis of the major disturbances that occurred during the last decade, such as the North America blackout of 2003 and the UCTE system disturbance of 2006, shows that failures or inadequacies in the Information and Communication Technology (ICT) infrastructure and also human errors had a significant impact on most of these blackouts.The aim of this thesis is to evaluate the contribution of these non-electrical events to the risk of power system blackouts. As the nature of these events is probabilistic and not deterministic, different probabilistic techniques have been developed to evaluate their impact on power systems reliability and operation.In particular, a method based on Monte Carlo simulation is proposed to assess the impact of an ICT failure on the operators’ situation awareness and consequently on their performance during an emergency. This thesis also describes a generic framework using Markov modeling for quantifying the impact of insufficient situation awareness on the probability of cascading electrical outages leading to a blackout. A procedure based on Markov modeling and fault tree analysis is also proposed for assessing the impact of ICT failures and human errors on the reliable operation of fast automatic protection actions, which are used to provide protection against fast-spreading electrical incidents. The impact of undesirable interactions and the uncoordinated operation of these protection schemes on power system reliability is also assessed in this thesis.The simulation results of these probabilistic methods show that a deterioration in the state of the ICT infrastructure and human errors affect significantly the probability and severity of power system blackouts. The conclusion of the work undertaken in this research is that failures in all the components of the power system, and not just the “heavy electrical” ones, must be considered when assessing the reliability of the electrical supply.

The project, Spider III, presents architecture and protocol of a multi-agent-based internet distributed computing system, which provides a convenient development and execution environment for transparent task distribution, load balancing, and fault tolerance. Spider is an on going distribution computing project in the Department of Computer Science, California State University San Bernardino. It was first proposed as an object-oriented distributed system by Han-Sheng Yuh in his master's thesis in 1997. It has been further developed by Koping Wang in his master's project, of where he made large contribution and implemented the Spider II System.

The Diploma work deals with the implementation of LTE Cat-M technology in the simulation tool Network Simulator 3 (NS-3). The work describe LPWA technologies and their use cases. In first are described the main parts of the Internet of Things (IoT) and Machine-to-Machine (M2M) communication. Subsequently are described and defined the most used technologies in LPWA networks. Technologies which are used in the LPWA networks are Sigfox, LoRaWAN, Narrowband IoT (NB-IoT) and Long Term Evolution for Machines (LTE Cat-M), where LTE Cat-M technology is described in more details. Simulations are simulated in simulation tool NS-3 and use LENA module. In NS 3 tool are simulated Simulations, which give us informations of Network state according to different Network set up. At the end are done changes of Radio Resource Control (RRC) states in NS-3 tool. These changes are required for correct implementation LTE Cat-M technology in NS-3 tool. Then we are able to simulate simulations, which meet to definition of LTE Cat-M technology.

The goal of this master's thesis is to describe geolocation techniques in wireless wide-area networks and the ways of expressing the individual node location. Practical part describes implementation of web services that simulate the node movement in these wireless networks and implementation of web service that is going to agregate the coordinate systems of these wireless networks.