This thesis proposes a high efficiency driving circuit for multiple light emitting diode (LED) lamps with dimming feature. The driving circuit consists of essentially a high-frequency half-bridge series resonant inverter with multiple output transformers, on which primary windings are connected in series, while secondary sides are loaded by LED lamps rated at different powers with different turn ratios. By controlling the frequency of the inverter, the resonant current as well as the lamp current can be regulated simultaneously. On the other hand, the LED lamps can be dimmed individually by the associated dimming switches with integral cycle control. The tactful circuit ensures a high circuit efficiency owing to less conducting losses and zero-voltage switching (ZVS) operation of the active power switches of the inverter and zero current switching (ZCS) operation of the dimming switches. Two prototype circuits designed for 60 W three RGB LED lamps and 50 W five white light LED lamps have been built and tested to verify the analytical predictions. Experimental results demonstrate that the driving circuit can operate the LED lamps at a high efficiency with a wide dimming range. The lamp power can be dimmed to 10% with frequency control, while whole dimming range can be achieved with integral cycle control. The circuit efficiency with integral cycle control is relatively higher than that with frequency control. The measured efficiencies for the two designed circuit are 93% and 90%, respectively, under the rated powers.

A high-frequency half-bridge series resonant inverter with multiple output transformers is developed for driving multiple cold-cathode fluorescent lamps (CCFLs) with dimming feature. The primary sides of the transformers are connected in series with the resonant inverter to have an identical current, while the secondary sides are loaded by CCFLs with galvanic isolation to each other. To ensure a high circuit efficiency, the active power switches of the inverter are designed to be switched on at zero voltage. The resonant current of the inverter can be regulated by controlling the switching frequency of the inverter, so that all CCFLs can be dimmed simultaneously. On the other hand, the primary sides of the output transformers are associated with parallel switches to dim the CCFLs individually. These dimming switches are operated at a low frequency by integral cycle control with zero current switching (ZCS) to reduce the switching losses. The resonant circuit is tactfully designed to alleviate the variation of the resonant current caused by the switching of dimming switches. A laboratory circuit is built for driving 5 CCFLs. The intended circuit performances are confirmed by test results. The variation of the resonant current is less than 10% when the dimming switches are switching, and the measured efficiency for the circuit is 96.15% under the rated powers.

An efficient Light Emitting Diode (LED) lamp driver circuit is proposed for retrofitting the conventionally used incandescent lamps with existing TRIAC dimmer. The dimming feature in a wide range of firing angle from 30¢X to 130¢X can be accomplished by means of double pulse-width modulation (DPWM) and analog current regulation. The LED lamp driver adopts a flyback converter with an auxiliary active power MOSFET for synchronous switch and an associated inductor for zero voltage switching (ZVS), leading to lower switching loss and thus achieving a higher circuit efficiency. In the thesis, the mode operation of the driver circuit is analyzed and the design equations are derived accordingly. A laboratory circuit is designed for an 50 W LED lamp which is composed of 45 high-brightness white LEDs in series. Experiments are carried out to test the circuit performances with two dimming schemes. The experimental results indicate that the driver can achieve a circuit efficiency of 95 % at the rated output. When the LED lamp is dimmed, the circuit efficiency with DPWM is higher than that with the analog current regulation. On the other hand, the LED lamp dimmed by analog current regulation has a higher efficiency but a less color shift by DPWM.

This work developed a deep investigation about different three level three level modulation patterns that the DAB converter can operate, and the impact of these different patterns over the converter power flow and efficiency. The DAB converter can be controlled by three design variables, here defined as control trio (D1, D2, φ). D1 is the duty cycle applied to the high voltage Full Bridge, D2 is the duty cycle applied to the low voltage Full Bridge and φ is the angle between the voltages. For the selection of the control trio that allow the current flow reduction and the efficiency maximization, two algorithms based on the sweep of these variables have been developed. First, the switching frequency (fs), the transformation ratio (a) and the inductance (LHV) are defined by the weighted average efficiency (standards) which result in an optimum design (maximum efficiency) considering the transformer load curve. On the second algorithm, one figure of merit is used, here called current factor , which finds the control trio to mitigate the power flow for each operation point, specified by input and output voltages and power. As result, this work figures out the best relation of design parameters (fs, a, LHV) and of the control trio (D1, D2, φ) for all the operation range (power and voltages variations in a defined period) that results in a maximum efficiency to the DAB converter, according with the component technologies. An analysis of the conditions to get zero voltage switching on semiconductors is also performed. / Este trabalho realiza uma investigação aprofundada sobre os diferentes padrões de modulação três níveis três níveis que o conversor DAB pode assumir, e o impacto que esses diferentes padrões provocam sobre a energia circulante na estrutura e sobre o rendimento. O conversor DAB pode ser controlado por três variáveis de projeto, aqui definidos como trio de controle (D1, D2, φ). D1 é a razão cíclica aplicada ao Full Bridge do lado de alta tensão, D2 a razão cíclica aplicada ao Full Bridge do lado de baixa tensão e φ o ângulo de defasagem entre as duas tensões. Para a seleção do trio de controle que permita a redução da corrente circulante e a maximização do rendimento, foram desenvolvidos dois algoritmos baseados na varredura destas variáveis. No primeiro, através do rendimento médio ponderado (normatizado), são encontradas a frequência de comutação (fs), a relação de transformação (a) e a indutância (LHV) que resulta em um projeto ótimo (máximo rendimento) considerando a curva de carga do transformador. Já, no segundo algoritmo, é utilizada uma figura de mérito, aqui denominada de fator de corrente que encontra o trio de controle que mitiga a energia circulante para cada ponto de operação especificado pelas tensões de entrada e saída e potência. Como resultado final, este trabalho aponta a melhor combinação de parâmetros de projeto (fs, a, LHV) e do trio de controle (D1, D2, φ) para toda a faixa de operação (variações de tensões e potências no período de tempo) que implica no máximo rendimento do conversor DAB, de acordo com as tecnologias. Também é realizada uma análise das condições a serem satisfeitas para que a comutação das chaves ocorra sob zero de tensão.

No description available.

Isolated inverter can provide galvanic isolation which is necessary for some applications with safety regulations. Traditionally, a two-stage configuration is widely applied with isolated dc-dc stage and a sinusoidal pulse-width-modulated (SPWM) dc-ac stage. However, this two-stage configuration suffers from more components count, more complex control and tend to have lower efficiency and lower power density. Meanwhile, a large dc bus capacitor is needed to attenuate the double line frequency from SPWM for two-stage configuration. Therefore, the single-stage approach including an isolated dc-rectified sine stage and a line frequency unfolder is preferable. Since the unfolder circuit is at line frequency being almost lossless, the isolated dc-rectified sine stage becomes critical. However, the relevant research for the single-stage isolated inverter is limited. People either utilize PWM based converter as dc-rectified sine stage with duty cycle adjustment or apply SRC or LLC resonant converter for better soft switching characteristics. For PWM based converter, hard switching restricts the overall inverter efficiency, while for SRC/LLC, enough wide voltage gain range and full range ZVS are the major issues. This dissertation aims to provide solutions for a high-efficiency, high-frequency resonant converter based single-stage soft-switching isolated inverter design. The LLC and LCLCL resonant converters are applied as the isolated dc-rectified sine stage with variable frequency modulation (VFM). Therefore, the rectified sine wave generation consists of many dc-dc conversion with different switching frequencies and an efficient dc-rectified sine stage design needs each dc-dc conversion to be with high efficiency. This dissertation will first propose the optimization methods for LLC converter dc-dc conversion. ZVS models are derived to ensure fully ZVS performance for primary side GaN devices. As a large part in loss breakdown, the optimization for transformer is essential. The LLC converter can achieve above 99% efficiency with proposed optimization approach. Moreover, the channel turn-off energy model is presented for a more accurate loss analysis. With all the design and optimization considerations, a MHz LLC converter based isolated inverter is designed and a hybrid modulation method is proposed, which includes full bridge (FB) VFM for output high line region and half bridge (HB) VFM for output low line region. By changing from FB to HB, the output voltage gain is reduced to half to have a wider voltage gain range. However, the total harmonic distortion (THD) of output voltage at light load will be impacted since the voltage gain will be higher with lighter load at the maximum switching frequency. A MHz LCLCL converter based isolated inverter is proposed for a better output voltage THD at light load conditions. The paralleled LC inside the LCLCL resonant tank can naturally create a zero voltage gain point at their resonant frequency, which shows superior performance for rectified sine wave generation. Besides the better THD performance, the LCLCL converter based isolated inverter also features for easier control, better ZVS performance and narrower switching frequency range. Meanwhile, the LCLCL based inverter topology has bi-directional power flow capability as well. With variable frequency modulation for ac-dc, this topology is still a single-stage solution compared to the traditional two-stage solution including PFC + LLC configuration. / Doctor of Philosophy / Inverters can convert dc voltage to ac voltage and typically people use two-stage approach with isolated dc-dc stage and dc-ac stage. However, this two-stage configuration suffers from more components count, more complex control and tend to have lower efficiency and lower power density. Therefore, the single-stage solution with dc-rectified sine wave stage and a line frequency unfolder becomes appealing. The unfolder circuit is to unfold the rectifier sine wave to an ac sine wave at the output. Since the unfolder is at line frequency and can be considered lossless, the key design is for the dc-rectified sine stage. The resonant converter featured for soft switching seems to be a good candidate. However, the inverter needs soft switching for the whole range and an enough wide voltage gain, which makes the design difficult, especially the target is high efficiency for the overall inverter. This dissertation aims to provide solutions for a high-efficiency, high-frequency resonant converter based single-stage soft-switching isolated inverter design. The LLC and LCLCL resonant converters are applied as the isolated dc-rectified sine stage with variable frequency modulation (VFM). Therefore, the rectified sine wave generation consists of many dc-dc conversion with different switching frequencies and an efficient dc-rectified sine stage design needs each dc-dc conversion to be with high efficiency. The design considerations and optimization methods for the LLC dc-dc conversion are firstly investigated. Based on these approaches, a MHz LLC converter based isolated inverter is designed with proposed hybrid modulation method. To further improve the light load performance, a MHz LCLCL converter based isolated inverter topology is proposed. The paralleled LC inside the LCLCL resonant tank can naturally create a zero voltage gain point which shows superior characteristics for rectified sine wave generation. Moreover, the LCLCL resonant converter based topology has bi-directional capability as well so it can work well for ac voltage to dc voltage conversion.

Boost dc-to-dc converters have very good source interface properties. The input inductor makes the source current smooth and hence these converters provide very good EMI performance. On account of this good property, the boost converter is also the preferred converter for off-line UPF rectifiers. One of the issues of concern in these converters is the large size of the storage capacitor on the dc link. The boost converter suffers from the disadvantage of discontinuous current injected to the load. The size of the capacitor is therefore large. Further, the ripple current in the capacitor is as much as the load current; hence the ESR specification of the tank capacitor is quite demanding. This is specially so in the emerging application areas of automotive power conversion, where the input voltage is low (typically 12V) and large voltage boost (4 to 5) are desired. The first part of this thesis suggests multi-phase boost converter to overcome the disadvantages of large size storage capacitor in boost converter. Comparison between the specification of single stage and multi-stages is thoroughly examined. Besides the average small signal analysis of N converters in parallel and obtaining an equivalent second order system are discussed. By paralleling the converters the design of closed loop control is a demanding task. To achieve proper current sharing among the stages using current control method is inevitable. Design and implementation of closed loop control of multi-phase boost converter both in analog and digital is the topic of next part of the thesis. Comparison between these two approaches is presented in this part and it will be shown that digital control is more convenient for such a topology on account of the requirement of synchronization, phase shifted operation, current balancing and other desired functions, which will be discussed later in detail. A new direct digital control method, which is simple and fast, is developed. Two different realizations with DSP controller and FPGA controller are considered. In the last part of the thesis a novel soft switching circuit for boost converter is presented. It provides Zero Voltage Switching (ZVS) for the main switch and Zero Current Switching (ZCS) for the auxiliary switch. The paper presents the idealized analysis giving all the circuit intervals and the equations necessary for the design of such a circuit. The proposed soft switching circuit is particularly suited for the tapped-inductor boost circuit with a minimum number of extra components. Extension of the method to tapped inductor boost converter addresses the application of Zero Voltage Transition (ZVT) to high conversion ratio converters. Extension of the method to multiphase boost converter shows that with less number of auxiliary switches soft switching operation can be achieved for all interleaved switching devices. Several laboratory prototype boost converters have been built to confirm the theoretical results and design methods are matching with both simulation and experimental results.

With the increasing demand for fast, cheaper, and efficient power converters come the need for a single-stage power factor correction (PFC) converter. Various single-stage PFC converter proposed in the literature has the drawback of high DC bus voltage at the input side and together with the shift to wide bandgap switches like GaN drives the converter cost higher. However, an interleaved topology with high-frequency isolation was proposed in this research work due to the drastic reduction in the DC bus voltage and extremely low input current ripple thereby making the need for an EMI filter circuit optional.   Meanwhile, this research work focuses on adapting the proposed topology for a high voltage low current application (EV charger - 400V, 7KW) and low voltage high current application (telecom power supply - 58V,  58A) owing to cost benefits. However, all single-stage PFC are faced with the drawback of second-order (100Hz) output harmonic ripple. Therefore, the design and simulation presented a huge peak to peak ripple of about 50V/3A and 26V/26A for the EV charger and telecom power supply case, respectively. This created the need for the design of a ripple cancellation circuit as the research required a peak to peak ripple of 8V and 200mV for the EV - charger and telecom power supply, respectively.   A novel output passive ripple cancellation technique was developed for the EV charger case due to the ease it offers in terms of control, circuit complexity and extremely low THDi when compared with the active cancellation approach. The ripple circuit reduced the 50V ripple to 431mV with the use of a total of 2.2mF capacitance at the output stage.   Despite designing the passive technique, an active ripple cancellation circuit was designed using a buck converter circuit for the telecom power supply. The active approach was chosen because the passive has a slow response and incurs more loss at a high current level. Adding the active ripple cancellation circuit led to a quasi-single stage LLC PFC converter topology. A novel duty-ratio feedforward control was added to synchronize the PFC control of the input side with the buck topology ripple cancellation circuit. The addition of the ripple circuit with the feedforward control offered a peak to peak ripple of 6.7mV and a reduced resonant inductor current by half.   After analysis, an extremely low THDi of 0.47%, PF of 99.99% and a peak efficiency of 97.1% was obtained for the EV charger case. The telecom power supply offered a THDi of 2.3%, PF of 99.96% with a peak efficiency of 95%.