ITC/USA 2011 Conference Proceedings / The Forty-Seventh Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2011 / Bally's Las Vegas, Las Vegas, Nevada / Acquisition based on Fast Fourier Transform (FFT) can acquire Pseudo-random code phase quickly and improve the performance of the satellite navigation receivers. In the paper Real-time receiver adopts the FPGA to realize the function of FFT and uses DSP processor to control the implementation process of Acquisition. For increasing the sensitivity of Acquisition incoherent accumulation were used in the process. Also, in the paper we have discussed the process method for decreasing the negative influence of signal power changes and carrier's Doppler frequency.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / The GPS receiver based on software radio technology is a kind of general purpose GPS signal processing platform which makes use of advanced design ideas and advanced design tools nowadays. We used FPGA device and lots of necessary peripherals such as DSP and PCI controller in our design to promote flexibility and practicability effectively. Various fast acquisition means and accurate tracking algorithms could be realized, improved and validated on this platform, besides basic GPS receiver function.

In this thesis, we discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance, and the data (information bit) rate. In order to decrease the latency a parallelized decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantization scheme and normalization approximations, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.

Orientador: Luis Eduardo Evangelista de Araujo / Tese (doutorado) - Universidade Estadual de Campinas, Instituto de Fisica Gleb Wataghin / Made available in DSpace on 2018-08-14T22:09:31Z (GMT). No. of bitstreams: 1 Soares_AntonioAugusto_D.pdf: 11187832 bytes, checksum: 3ffb3d078fef8dd053b760fc0342ec6f (MD5) Previous issue date: 2009 / Resumo: Nesta tese apresentamos um estudo teórico da interação coerente entre trens de pulsos ultracurtos e sistemas atômicos simples de dois e três níveis, este último na configuração L. Primeiramente avaliamos a situação em que um trem de pulsos ultracurtos não só sonda um sistema de três níveis na configuração L, mas também leva o átomo à configuração do átomo vestido. Nessas condições estudamos o efeito do acúmulo coerente de excitação na transparência eletromagneticamente induzida (EIT) experimentada pelo trem de pulsos ultra-curtos. Mostramos que os parâmetros do trem de pulsos ( área do pulso, diferença de fase entre pulsos consecutivos e período de repetiçãco dos pulsos) determinam a dinâmica da formação da EIT. Em seguida estudamos os efeitos da propagação do trem de pulsos ultracurtos através de um meio atômico estendido, constituído por sistemas de dois e três níveis na configuraçãco L. Mostramos que no caso em que o meio é constituído por sistemas de dois níveis a frequência central dos pulsos é rapidamente removida devido à propagação, prejudicando o efeito de acúmulo coerente. Já para o meio constituído por sistemas de três níveis o efeito acumulativo é observado e coerência é transferida ao meio, levando a uma sobreposição linear entre os níveis fundamentais, sobreposição esta que está associada à formação da EIT. Após um número suficientemente grande de pulsos o meio se torna transparente aos pulsos subsequentes que se propagam sem sofrer alterações em seu perfil temporal e espectral. Outra situação que estudamos nesta tese é aquela onde o sistema atômico é excitado por um campo contínuo monocromático levando o átomo à configuração do "átomo vestido". Este sistema é, então, investigado por um trem de pulsos ultracurtos. Neste caso mostramos que a utilização do trem de pulsos ultracurtos permite a realização de espectroscopia de alta resolução dos estados atômicos vestidos induzidos pelo campo contínuo monocromático / Abstract: In this thesis we present a theoretical study about the coherent interaction between a train of ultrashort pulses with two- and three-level atomic systems, this last in the L configu-ration. Firstly, we investigated the situation at which a train of ultrashort pulses not only probes the three-level system in the L configuration, but also drives the atom to its dressed configura-tion. Under these conditions, we studied the effects of the coherent accumulation of excitation on the electromagnetically induced transparency (EIT) of the train of ultrashort pulses. We showed that the pulse train parameters (area, repetition period, and phase between successive pulses) play a significant role in establishing EIT. Then, we study the effects of propagation through an extended sample of two- and three-level atoms. We showed that in the two-level case, absorption of the pulse¿s resonant frequency by the atoms quickly compromises the accumulation of excitation. In the three-level case, the accumulative effect occurs, and the pulse train transfers coherence between the two lower states of the atoms, driving population into a dark superposition state. Such a superposition is related to the EIT formation and after a large enough number of pulses, the medium becomes transparent to the driving pulses. Later pulses in the train propagate through the atomic medium with both their amplitude and temporal profile preserved. Another configuration that we investigated in this thesis is that at which the atomic system is excited by a monochromatic cw laser that drives the atom to its dressed configuration. Such a system is then probed by an ultrashort pulse train. In this case, we showed that an ultrashort pulse train can be used to perform high-resolution spectroscopy of dressed atomic states / Doutorado / Física Atômica e Molecular / Doutor em Ciências

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This research focuses on a novel integrated approach for computing and representing complex numbers as a single entity without the use of any dedicated multiplier for calculating the fast Fourier transform algorithm (FFT), using the Distributed Arithmetic (DA) technique and Complex Binary Number Systems (CBNS). The FFT algorithm is one of the most used and implemented technique employed in many Digital Signal Processing (DSP) applications in the field of science, engineering, and mathematics. The DA approach is a technique that is used to compute the inner dot product between two vectors without the use of any dedicated multipliers. These dedicated multipliers are fast but they consume a large amount of hardware and are quite costly. The DA multiplier process is accomplished by shifting and adding only without the need of any dedicated multiplier. In today's technology, complex numbers are computed using the divide and conquer approach in which complex numbers are divided into two parts: the real and imaginary. The CBNS technique however, allows for each complex addition and multiplication to be computed in one single step instead of two. With the combined DA-CBNS approach for computing the FFT algorithm, those dedicated multipliers are being replaced with a DA system that utilize a Rom-based memory for storing the twiddle factor 'wn' value and the complex arithmetic operations being represented as a single entity, not two, with the CBNS approach. This architectural design was implemented by coding in a very high speed integrated circuit (VHSIC) hardware description language (VHDL) using Xilinx ISE design suite software program version 14.2. This computer aided tool allows for the design to be synthesized to a logic gate level in order to be further implemented onto a Field Programmable Gate Array (FPGA) device. The VHDL code used to build this architecture was downloaded on a Nexys 4 DDR Artix-7 FPGA board for further testing and analysis. This novel technique resulted in the use of no dedicated multipliers and required half the amount of complex arithmetic computations needed for calculating an FFT structure compared with its current traditional approach. Finally, the results showed that for the proposed architecture design, for a 32 bit, 8-point DA-CBNS FFT structure, the results showed a 32% area reduction, 41% power reduction, 59% reduction in run-time, 42% reduction in logic gate cost, and 66% increase in speed. For a 28 bit, 16-point DA-CBNS FFT structure, its area size, power consumption, run-time, and logic gate, were also found to be reduced at approximately 30%, 37%, 60%, and 39%, respectively, with an increase of speed of approximately 67% when compared to the traditional approach that employs dedicated multipliers and computes its complex arithmetic as two separate entities: the real and imaginary.

Speeding up addition is the key to faster digital signal processing (DSP). This can be achieved by exploiting the properties of redundant number systems. Their expanded symbol (digit) alphabet gives them multiple representations for most values. Utilising redundant representations at the output of an adder permits addition to be performed without carry-propagation, yielding fast, constant time performance irrespective of the word length. A resource efficient implementation of this fast adder structure is developed that re-purposes the fast carry logic of low-cost field programmable gate arrays (FPGAs). Experiments confirm constant time addition and show that it outperforms binary ripple carry addition at word lengths of greater than 44 bits in a Xilinx Spartan 3 FPGA and 24 bits in an Altera Cyclone III FPGA. Redundancy also provides other properties that can be exploited for performance gain. Some redundant representations will have more zero-symbols than others. These maximise the opportunities to exploit the multiplicative absorbing and additive identity properties of zero that when exercised reduce superfluous calculations. A serial recoding algorithm is developed that generates a redundant representation for a specified value with as few nonzero symbols as possible. Unlike previously published methods, it accepts a wide specification of number systems including those with irregularly spaced symbol alphabets. A Markov analysis and analysis of the elementary cycles in the formulated state machine provides average and worst case measures for the tested number system. Typically, the average number of non-zero symbols is less than a third and the worst case is less than a half. Further to the increase in zero-symbols, zero-dominance is proposed as a new property of redundant number representations. It promotes a set of representations that have uniquely positioned zero-symbols, in a Pareto-optimal sense. This set covers all representations of a value and is used to select representations to optimise the calculation of a dot-product. The dot-product or vector-multiply is a fundamental operation in DSP, since it is employed in filtering, correlation and convolution. The nonzero partial products can be packed together, substantially reducing the calculation time. The application of redundant number systems provides a two-fold benefit. Firstly, the number of nonzero partial products is reduced. Secondly, a novel opportunity is identified to use the representations in the zero-dominant set to optimise the packing further, gaining an extra 18% improvement. An implementation of the proposed dot-product with partial product packing is developed for a Cyclone II FPGA. It outperforms a quad-multiplier binary implementation in throughput by 50% . Redundant number systems excel at increasing performance in particular DSP subsystems, those that are numerically intensive and consist of considerable accumulation. The conversion back to a binary result is the performance bottleneck in the DSP algorithm, taking a time proportional to a binary adder. Therefore, redundant number systems are best utilised when this conversion cost can be amortised over many fast redundant additions, which is typical in many DSP and communications applications.

Digital technology has made complex signal processing possible in communication systems and greatly improved the performance and quality of most modern telecommunication systems. The telecommunication industry and specifically mobile wireless telephone and computer networks have shown phenomenal growth in both the number of subscribers and emerging services, resulting in rapid consumption of common resources of which the electromagnetic spectrum is the most important. Technological advances and research in digital communication are necessary to satisfy the growing demand, to fuel the demand and to exploit all the possibilities and business opportunities. Efficient management and distribution of resources facilitated by state-of-the-art algorithms are indispensable in modern communication networks. The challenge in communication system design is to construct a system that can accurately reproduce the transmitted source message at the receiver. The channel connecting the transmitter and receiver introduces detrimental effects and limits the reliability and speed of information transfer between the source and destination. Typical channel effects encountered in mobile wireless communication systems include path loss between the transmitter and receiver, noise caused by the environment and electronics in the system, and fading caused by multiple paths and movement in the communication channel. In multiple access systems, different users cause interference in each other’s signals and adversely affect the system performance. To ensure reliable communication, methods to overcome channel effects must be devised and implemented in the system. Techniques used to improve system performance and capacity include temporal, frequency, polarisation and spatial diversity. This dissertation is concerned mainly with temporal or time diversity. Channel coding is a temporal diversity scheme and aims to improve the system error performance by adding structured redundancy to the transmitted message. The receiver exploits the redundancy to infer with greater accuracy which message was transmitted, compared with uncoded systems. Sparse graph codes are channel codes represented as sparse probabilistic graphical models which originated in artificial intelligence theory. These channel codes are described as factor graph structures with bit nodes, representing the transmitted codeword bits, and bit-constrained or check nodes. Each constraint involves only a small number of code bits, resulting in a sparse factor graph with far fewer connections between bit and check nodes than the maximum number of possible connections. Sparse graph codes are iteratively decoded using message passing or belief propagation algorithms. Three classes of iteratively decodable channel codes are considered in this study, including low-density parity-check (LDPC), Turbo and repeat-accumulate (RA) codes. The modulation platform presented in this dissertation is a spectrally efficient wideband system employing orthogonal complex spreading sequences (CSSs) to spread information sequences over a wider frequency band in multiple modulation dimensions. Special features of these spreading sequences include their constant envelopes and power output, providing communication range or device battery life advantages. This study shows that multiple layer modulation (MLM) can be used to transmit parallel data streams with improved spectral efficiency compared with single-layer modulation, providing data throughput rates proportional to the number of modulation layers at performances equivalent to single-layer modulation. Alternatively, multiple modulation layers can be used to transmit coded information to achieve improved error performance at throughput rates equivalent to a single layer system / Dissertation (MEng (Electronic Engineering))--University of Pretoria, 2007. / Electrical, Electronic and Computer Engineering / unrestricted