Le projet de thèse porte sur l'oscillateur harmonique; l'oscillateur dépend du signal de fréquence fondamentale à 25 GHz, qui est amplifié à l'aide d'un LNA et d'un amplificateur de puissance afin de générer un troisième signal harmonique à 75 GHz en sortie et de faire une contre-réaction du signal fondamental afin d'assurer la continuité de l'oscillation. Un diplexeur est utilisé pour séparer les deux fréquences à l’étage de sortie, en tenant compte de l’amélioration de la puissance de sortie, du bruit de phase et de l’efficacité de puissance ajoutée PAE à la fréquence candidate de l’application 5G. La technologie de transistor choisie est le FDSOI 28 nm de STMicroelectronics. / The PhD project is about harmonic oscillator; the oscillator depends on the fundamental frequency signal at 25 GHz which is amplified using an LNA and power amplifier in order to generate third harmonic signal at 75 GHz at the output, and feedback the fundamental signal to ensure the continuity of the oscillation. A diplexer is used to separate between both frequencies at the output stage, taking in consideration the improvement of the output power, phase noise, and the power added efficiency PAE at the candidate frequency of 5G application. The transistor technology chosen is the 28nm FDSOI from the STMicroelectronics.

[pt] O presente trabalho apresenta uma estrutura balanceada em quadratura para linearização de amplificadores de potência em RF e microondas. Várias técnicas de linearização têm sido utilizadas para reduzir a intermodulação. Alguns exemplos, tais como Feedback, Pre-distorsion e Feedforward, podem ser mencionados. A característica ímpar de nosso arranjo é que ele não precisa de ajustes, enquanto que os outros métodos precisam. A desvantagem de nosso arranjo é que ele reduz apenas os produtos de intermodulação de terceira ordem. Um trabalho prático foi conduzido, mostrando que nosso arranjo é capaz de reduzir o conteúdo de intermodulação de terceira ordem em até 17 dB. / [en] The present work introduces a quadrature balanced structure for linearization of RF and microwave amplifiers. Several linearization techniques have been used to reduce intermodulation products. Some examples such as Feedback, Pre-distorsion and Feedforward may be mentioned. The unique feature of our arrangment is that it does not need adjustments, while the other methods do. The drawback of our arrangement is that it only reduces the third-order intermodulation products. A pratical work was carried out, showing that our arrangement is able to reduce the third-order intermodulation content up to 17 dB. / [es] EL presente trabajo presenta una extructura balanceada en cuadratura para linealización de amplificadores de potencia en RF y microondas. Varias técnicas de linealización han sido utilizadas para reducir la intermodulación. Algunos ejemplos como Feedback, Pre-distorsion y Feedforward, pueden ser mencionados. La principal ventaja de nuestro arreglo frente a los otros métodos es que éste no precisa de ajustes. La desventaja de nuestro arreglo es que reduce solamente los produtos de intermodulación de tercer orden. Se condujo un trabajo práctico, mostrando que nuestro arreglo es capaz de reducir el contenido de intermodulación de tercera orden en hasta 17 dB.

Spin Torque Oscillator (STO) is a promising technology for microwave and radar applications due to its large tunability, miniature size, high operation frequency, high integration level, etc. However, the technology comes also with issues and challenges,such as low output power and spectrum impurity. For instance, in order to apply the STO technology into communication systems, an amplifier is required to compensate the STO’s low output power.     This thesis presents an amplifier for promising Magnetic Tunnel Junction (MTJ) STO devices. The motional resistance of different MTJ STO devices varies from several Ohms to hundreds Ohms, which makes the design challenging. This thesis focuses first on extracting the amplifier requirements using the state-of-the-art MTJ STO devices. The operation frequency of MTJ STO is in the range of 4-8GHzwith a -40～-60 dBm output power. Therefore, a wideband amplifier with 45-65 dB gain is required. Then based on the amplifier requirements, an amplifier topology is proposed, which is composed of two types of input balun-LNA stages depending onthe motional resistance of the STO, a broadband limiting amplifier and an outputbuffer. CG-CS architecture is suitable for the input balun-LNA in the small motional resistance case and cascoded-CS architecture is suitable for the large motional resistance case. The limiting amplifier and the output buffer are the common circuits shared by two cases via switches.     The wideband amplifier for STO is implemented using a 65nm CMOS process with 1.2 V supply and it exhibits 52.36 dB gain with 1.34-11.8 GHz bandwidth insmall motional resistance case and 59.29 dB gain with 1.171-8.178 GHz bandwidth in large motional resistance case. The simulation results show that the amplifier has very low power consumption and meets the linearity and noise performance requirements.

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As we move under the aegis of the Moore's law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node.

A spatial soliton is a shape invariant self guided beam of light or a self induced waveguide. Spatial solitons appear as a result of the balance of diffraction and nonlinear focusing in a system. They have been observed in many different conservative media in the last couple of years. Solitons are ubiquitous, because of the probability of using their interactions in optical data processing, communications etc. Up to now due to the power required to generate the solitons, and the response times of the soliton supporting media, these special waves of nature could not penetrate the applications arena. Semiconductors, with their resonant nonlinearities, are thought to be ideal candidates for fast switching, low power spatial solitons. In this dissertation it is shown theoretically and experimentally that it is possible to observe stable spatial solitons in a periodically patterned semiconductor optical amplifier (PPSOA). The solitons have unique beam profiles that change only with system parameters, like pumping current, etc. Their coherent and incoherent interactions which could lead to all optical devices have been investigated experimentally and theoretically. The formation of filaments or modulational instability has been studied theoretically and yielded analytical formulae for evaluating the filament gain and the maximum spatial frequencies in PPSOA devices. Furthermore, discrete array amplifiers have been analyzed numerically for discrete solitons, and the prospect of using multi peak discrete solitons as laser amplifiers is discussed.

Class C power amplifiers offer higher efficiency than class B power amplifiers, but suffer from poor linearity. A feedback based biasing system to improve the linearity of a class C power amplifier is designed. A class B amplifier with a gain of 20 dB and 20 MHz bandwidth at 900 MHz acts as the launching point for the design. The biasing and output network of the class B power amplifier is modified to produce a class C amplifier at conduction angles of 180°, 162°, 126°, 90°, and 54°. A feedback based biasing system, which uses two matched and scaled down transistors, compares the DC current of a class B and a class C biased transistor. This comparison is used to control the biasing voltage of the amplifier. The performance for each class C amplifier is simulated with the proposed constant conduction angle biasing (CCAB) system. The conduction angle, transducer gain, operational gain, VSWR, and drain efficiency are measured from simulation for each of the 5 normally biased and 5 CCAB amplifiers. Dynamic ranges of over 8 dB are demonstrated for the CCAB amplifiers. The effects of loop gain, temperature, and operating frequency for the 126° amplifier are simulated. The 3rd order intermodulation products of a 10 MHz AM modulated 900 MHz signal are compared for the 126° normally biased and CCAB biased amplifier as well as the class B amplifier. The difference between the fundamental and the 3rd order intermodulation products is shown to improve from 9.9 dB for the normal class C to 28.7 dB for the CCAB amplifier.

Charge detection is essential for a large number of commercial and scientific applications. A charge amplifier is one of the most fundamental building blocks for a detector system. This thesis describes the design, circuit implementation, and post-silicon testing of two different charge amplifier designs, analog and digital, that address some commonly seen fundamental challenges in the charge detection application. In particular, the proposed designs can be integrated with an image charge detector (ICD) to study the characteristics of dust on Mars. The proposed charge amplifier design utilizes a small 10 fF feedback capacitor to achieve a high gain. The fully integrated custom differential charge amplifier design improves the accuracy and robustness of its charge gain, and provides a compact method to extract detector capacitance for gain calibration. Conventional charge amplifiers' charge-to-voltage gain is a function of the detector parasitic capacitance. Therefore, a high precision photo-current calibration method is proposed here to enable an accurate gain calibration. In addition, a novel "digital amplifier" with close to rail-to-rail output swing is proposed to realize an infinite equivalent open-loop gain. Consisting of an ADC and charge pump as the amplifier core, this proposed design maintains a consistent closed-loop gain independent of the input parasitic capacitance. The ADC is realized as a single comparator, i.e. a 1-bit ADC, which, together with an SR latch and a differential charge pump, replaces the conventional analog amplifier core.