There are many kinds of commercial memory cards on the market. Due to great improvements in modern technology, they have great amounts of capacity, low power consumption, and are easily available. Therefore a data logging system using a commercial memory card is a convenient and economic procedure. This thesis introduces a wearable data logging system for physiological recording. A front-end amplifier, analog to digital converter, and a memory card controller compose the basis of this system. The front-end amplifier uses a switched-capacitor structure, so the output waveform is discrete in regard to the time domain. This brings an advantage in saving power for not keeping charging the load capacitance. Lateral bipolar transistors fabricated in a CMOS process are used as input devices. A conventional ADC is used to convert the amplified signal into digital data. Finally MultiMediaCard is chosen as a large storage space. This thesis contributes the analysis, design and measurement of the amplifier front-end. In addition, the design and implementation of a controller circuit for sequential data storage into the MultiMediaCard memory is described. Special attention was paid to achieving a small area, low-complexity and low-power implementation suitable for integration. Measured results obtained from a preliminary FPGA implementation are reported and the functionality of a complete logger circuit is demonstrated with measured results.

Due to variations in process, voltage, and temperature (PVT), amplifiers are almost solely designed for use in a negative feedback loop. The feedback loop mitigates the effect of PVT, however maintaining stability becomes the main design challenge. Further, multi-stage amplifiers with high open-loop gain are used for powering headphone speakers in modern portable electronics. As there are many different headphone manufacturers and compatibility specifications, headphone amplifiers are subjected to a wide variation in capacitive and resistive loads, which further complicates the stability upkeep. This thesis explores a two-stage (Common-Gate Feedback) and three-stage (Impedance Adapting Compensation) amplifier topology with respect to performance under wide load variations. For both compensation topologies, an analytical analysis is presented, followed by a design proposal for a headphone amplifier application. Finally, the trade-offs for maintaining stability under varying loads are discussed. / text

In the past decade, there has been great motivation to improve the efficiency of power amplifiers (PAs) in handset transmitter systems in order to address critical issues such as poor battery life and excessive heat. Currently, the focus lies on high data rate applications such as wideband code division multiple access (WCDMA) and long term evolution (LTE) standards due to the stringent efficiency and linearity requirements on the PA. This thesis describes a simulation-based study of techniques for enhancing the efficiency of a CMOS power amplifier for WCDMA and LTE applications. The primary goal is to study the concepts of envelope and average power tracking in simulation and to demonstrate the effectiveness of these supply modulation techniques on a CMOS PA design. The P1dB and IMD performance of a Class A/AB CMOS PA has been optimized to operate with high peak-to-average modulation with WCDMA and LTE signals. Behavioral models of envelope and average power tracking are implemented using proposed algorithms, and a system-level analysis is performed. Envelope tracking is seen to offer a peak PAE improvement of 15% for WCDMA, versus a fixed voltage supply, while average power tracking renders a maximum efficiency gain of 9.8%. Better than -33dBc adjacent channel leakage-power ratio (ACLR) at 5MHz offset and EVM below 4% are observed for both supply tracking techniques. For LTE, envelope and average power tracking contribute to a peak PAE enhancement of 15.3% and 7%, respectively. LTE ACLR begins failing the -30dBc specification above 22.5dBm output power during envelope tracking operation in the PA implementation described here. / text

Cobham Electronic Systems, Inc. has developed a field-programmable telemetry transmitter module for higher-power (0.1W to 25W) airborne telemetry applications. A key feature of the transmitter is high DC to RF conversion efficiency over the entire variable output power range of 25dB through the use of GaN amplifiers. This high efficiency is realized by using a variable voltage DC-DC converter and dynamic bias control of the GaN amplifier elements. This feature is useful in that output power can be tailored to mission requirements and timelines, thereby extending battery life and increasing operation time. The transmitter receives configuration commands and can be programmed through an external data port. The transmitter can be configured for RF power and frequency over the telemetry S-Band frequency range, and has multiple data rates. The unit consists of RF, digital and power supply circuits. The RF transmitter is a PCM-FM type with a phase-locked loop, driver amplifiers, a power amplifier and a digital processor for RF control. The unit contains a digital processor, FPGA's, and flash memory. The power supplies contains all the regulator circuits to supply power to the rest of the unit, variable output drain voltage to the GaN devices, EMI filtering, under/overvoltage protection, a temperature sensor and a digital processor for power control. The electronics are housed in a compact aluminum housing.

Jitter is generally defined as a time deviation of the clock waveform from its desired position. The deviation which occurs can be on the leading or lagging side and it can be bounded (deterministic) or unbounded (random). Jitter is a critical specification in the digital system design. There are various techniques to measure the jitter. The straightforward approach is based on spectrum analyzer or oscilloscope measurements. In this thesis an on-chip jitter measurement technique is investigated and the respective circuit is designed using 65 nm CMOS technology. The work presents the high level model and transistor level model, both implemented using Cadence software. Based on the Vernier concept the circuit is composed of an edge detector, two oscillators, and a phase detector followed by a binary counter, which provides the measurement result. The designed circuit attains resolution of 10ps and can operate in the range of 100 - 500 MHz Compared to other measurement techniques this design features low power consumption and low chip area overhead that is essential for built-in self-test (BIST) applications.

This work focuses on different kinds of Switch Mode Power Amplifiers (SMPAs) using LDMOS technologies. It involves a literature study of different SMPA concepts. Choosing the suitable class that achieves the high efficiency was the base stone of this work. A push-pull class J power amplifier (PA) was designed with an integrated LC resonator inside the package using the bondwires and die capacitances. Analysis and motivation of the chosen class is included. Designing the suitable Input/Output printed circuit board (PCB) external circuits (i.e.; BALUN circuit, Matching network and DC bias network) was part of the work. This work is done by ADS simulation and showed a simulated result of about 70% drain efficiency for 34 W output power and 16 dB gain at 2.14 GHz. Study of the losses in each part of the design elements is also included. Another design at lower frequency (i.e.; at 0.94 GHz) was also simulated and compared to the previous design. The drain efficiency was 83% for 32 W output power and 15.4 dB Gain.

This thesis starts with a discussion of different classes of operation of power amplifiers (PAs). Comparing advantages and disadvantages of these classes, class AB is chosen as the best initial candidate for the design of broadband PA. Different methods for design of matching networks are first discussed. Some of them fall into the group of narrowband matching networks, while others are suitable for a broadband context. Broadband design methodologies are categorized into two groups of real-to-real transformations and complex-to-real transformations. Complex-to-real transformations are the most useful methods for this project, since design of power amplifiers deals with complex loads rather than just real loads. The design of broadband matching networks exploiting filter theory is presented in this thesis for synthesizing broadband and highly efficient power amplifiers (PAs). Starting with sets of optimum impedances over the targeted frequency band, the matching networks are designed using a systematic approach. The effects of load termination at the 2nd and 3rd harmonic on the PA performance (efficiency) are studied. The significance of proper termination, especially at the 2nd harmonic, is highlighted. To prevent further complication of the design process, though, specific harmonic termination (stubs) is avoided and special arrangement of the matching network (position of the bias network) is preferred, as it is found to lead to acceptable efficiency. Two PA prototypes were designed with the proposed methodology using 25W GaN devices. The designs targeted two frequency bands: 1.8 to 2.2 GHz (20% BW) and 1.8 to 2.7 GHz (40% BW). For the former, drain efficiency (DE) of 70% (+/–5%) and output power of 45.5 dBm (+/- 1.0dB) was measured while the latter achieved very promising efficiency of about 60% over the entire bandwidth.

The trade-off between linearity and efficiency is the key limiting factor to wideband power amplifier design. Current wireless research focuses much of its effort on building power amplifiers with the two aforementioned criteria going hand in hand to build an optimal design. This thesis investigates the sources of nonlinearity associated with GaN high electron mobility transistors (HEMT), and their subsequent effects on the linearity metrics of the power amplifier. The investigation began with an analysis of the sources of nonlinearity, and then a design-based approach to mitigate those sources of nonlinearity was developed. This design approach was compared with existing trends in power amplifier design. The device technology used in the design was CREE GaN HEMT (45W and 6W). In this report, a systematic approach to designing a two stage power amplifier is discussed, and analyzed for design of linear and highly efficient power amplifiers for base stations. The designed power amplifier consists of two stages: a driver stage and a power stage. The driver stage aimed to linearize the power stage by using circuit analysis and transistor properties along with providing the necessary gain. The power stage was built to complement the driver stage and to achieve high efficiency for the power amplifier. An inter-stage matching network placed between the two stages allowed for the required matching of impedances; transmission lines in the bias feed controlled the harmonic impedances for optimal performance without disrupting performance at fundamental frequencies. This approach effectively improved, and maintained, high efficiency over 200MHz of bandwidth. The design approach was simulated and fabricated in order to test the feasibility of linear power amplifier operation with the use of digital pre-distortion (DPD). The fabricated prototype achieved about 70% peak efficiency over the bandwidth and maintained linearity above 40dBc adjacent channel leakage ratio (ACLR) and below 3% error vector magnitude (EVM). The measurement results indicated that the need for DPD was eliminated when the power amplifier was operating in back-off at the center frequency (800MHz). This thesis compares the prototyped design with existing multistage designs which use linear drivers. The report provides conclusions derive from measurement results and bandwidth limitations faced throughout the course of the design. Lastly, potential research directions, which may allow researchers to overcome the limitations of this design, are discussed.

The purpose of this thesis is to linearize a power amplifier using digital predistortion. A power amplifier is a nonlinear system, meaning that when fed with a pure input signal the output will be distorted. The idea behind digital predistortion is to distort the signal before feeding it to the power amplifier. The combined distortions from the predistorter and the power amplifier will then ideally cancel each other. In this thesis, two different approaches are investigated and implemented on an FPGA. The first approach uses a nonlinear model that tries to cancel out the nonlinearities of the power amplifier. The second approach is model-free and instead makes use of a look-up table that maps the input to a distorted output. Both approaches are made adaptive so that the parameters are continuously updated using adaptive algorithms. First the two approaches are simulated and tested thoroughly with different parameters and with a power amplifier model extracted from the real amplifier. The results are shown satisfactory in the simulations, giving good linearization for both the model and the model-free technique. The two techniques are then implemented on an FPGA and tested on the power amplifier. Even though the results are not as well as in the simulations, the system gets more linear for both the approaches. The results vary widely due to different circumstances such as input frequency and power. Typically, the distortions can be attenuated with around 10 dB. When comparing the two techniques with each other, the model-free method shows slightly better results.

To allow access to the network at all times a base station has to continuously stay active. While being active, a base station does not usually transmit data constantly. Typically, the base stations either send out lots of data or barely anything at all, yet, the network is actively drawing power the whole time. Succeeding in lowering the power consumed when the data rate is often so low would therefore lead to great benefits, both economically and environmentally, as well as new prospects of innovation in engineering. The process of how to dynamically change from a capacity optimized mode to an energy optimized mode as well as when to do this change is studied in this thesis for LTE. By using methods such as antenna muting and psi-omni coverage, the power consumption can decrease. These solutions however also decreases performance, and has to be activated with great care in mind not to cause any major impact on user performance. The dynamic configuration is dependent on the load of the system, changing to an energy efficient mode when traffic is low and to a capacity optimized mode when the network needs to supply high data rates. Simulations show that most energy savings can be found in rural and urban environments. Dynamic antenna muting achieved, summarizing macro environments, 24.9% energy savings with 95.27% downlink data rates compared to the reference case of using sector mode continuously i.e MIMO. In the same environments, dynamic psi-omni coverage together with antenna muting achieved energy savings of 43.8% with 89.3% downlink data rates compared to typical sector mode. Traffic rates are based on future demands in Europe by 2015, assuming that 20% of the subscribers are downloading 900 MB/h and the other 80% subscribers, at 112.5 MB/h.