Thesis (M. Phil.)--University of Hong Kong, 2008. / Includes bibliographical references (leaf 100-105) Also available in print.

Thesis (Ph. D.)--Ohio State University, 2004. / Title from first page of PDF file. Document formatted into pages; contains xix, 156 p.; also includes graphics (some col.). Includes bibliographical references (p. 152-156).

Thesis (M.E.)--University of Canterbury, 2008. / Typescript (photocopy). "August 2008." Includes bibliographical references (p. [123]-126). Also available via the World Wide Web.

Thesis (Ph. D.)--Ohio State University, 2005. / Available online via OhioLINK's ETD Center; full text release delayed at author's request until 2008 Dec 1

Thesis (MScIng)--Stellenbosch University, 2008. / ENGLISH ABSTRACT: Modern communication systems demand efficient, linear power amplifiers. The amplifiers are often operated in the backed-off power levels at which linear amplifiers such as class B amplifier are particularly inefficient. The Doherty amplifier provides an improvement as it increases efficiency at backed of power levels. Doherty amplifiers consists of two amplifiers, a carrier amplifier and a peaking amplifier, of which the output is combined in a novel way. Implementation of the Doherty amplifier with transistors is not ideal. One of the main problems is the insufficient current production of the peaking amplifier at peak envelope power (PEP) if it is implemented as a class C amplifier. A suggested solution to this problem is a bias adaption system that controls the peaking amplifier gate voltage dynamically depending on the input power levels. The design and evaluation of such a adaptive Doherty amplifier is the main goal of this thesis. A classical Doherty amplifier with and an uneven Doherty amplifier with unequal power division between the carrier and peaking amplifiers are also evaluated and compared with the adaptive Doherty amplifier. The amplifiers are designed using a 10 W LDMOS FET device, the MRF282. The adaptive Doherty amplifier and the uneven Doherty amplifier show significant improvements in efficiency and output power over the even Doherty amplifier. At PEP the adaptive Doherty delivers 42.4 dBm at 39.75 % power added efficiency (PAE), the uneven Doherty amplifier 41.9 dBm at 40.75 % PAE and the even Doherty amplifier 40.8 dBm at 38.6 % PAE. At 3dB backed-off input power the adaptive Doherty amplifier has an efficiency of 34.3%, compared to 34.9 5% for the uneven Doherty amplifier and 29.75 % for the even Doherty amplifier. / AFRIKAANSE OPSOMMING: Moderne kommunikasie stelsels vereis effektiewe, linieêre drywing versterkers. Die versterkers word dikwels in laer drywings vlakke bedryf waar linieêre versterkers soos ’n klas B versterker besondere lae effektiwiteit het. Die Doherty versterker bied ’n uitweg omdat dit verbeterde effektiwiteit by lae drywings vlakke bied. ’n Doherty versterker bestaan uit twee versterkers, die hoof versterker en die aanvullende versterker, waarvan die uittrees met ’n spesiale kombinasie netwerk bymekaar gevoeg word. Die implementasie van Doherty versterkers met transistors is nie ideaal nie. Een van die hoof probleme is die onvoldoende stroom wat deur die aanvullings versterker gebied word by piek omhulsel drywing (POD). ’n Oplossing vir die probleem is om ’n aanpassings sisteem te gebruik wat die aanvullende versterker se hekspanning dinamies beheer afhangende van die intree drywings vlakke. Die ontwerp en evaluasie van so ’n aanpassings Doherty versterker is die hoof doel van hierdie tesis. ’n Klassieke Doherty versterke met gelyke drywings verdeling en ’n ongelyke Doherty versterker wat gebruik maak van ongelyke drywings verdeling tussen die hoof-en aanvullende versterkers is ook gevalueer en vergelyk met die aanpassings Doherty versterker. Die versterkers was ontwerp met ’n 10 W LDMOS FET, die MRF282. Die aanpassings Doherty versterker en die ongelyke Doherty versterker het aanmerklike verbeteringe in effektiwiteit en uittree drywing gebring in vergelyking met die ewe Doherty versterker. By POD het die aanpassings versterker 42.4 dBm teen 39.75 % drywing toegevoegde effektiwiteit (DTE) gelewer, die ongelyke Doherty versterker 41.9 dBm teen 40.75 % DTE, en die ewe Doherty versterker 40.8 dBm teen 38.6 DTE. By ’n intree drywingsvlak 3 dB laer as POD het die aanpassings Doherty versterker ’n effektiwiteit van 34.3 % getoon, in vergelyking met die onewe Doherty versterker se 34.9 % en die ewe Doherty versterker se 29.75 % DTE.

Compared to current single-standard radio solutions, multi-standard radio transceivers enable higher integration, backward compatibility and save power, area and cost. The primary bottleneck in their realization is the development of high-performance frequency-reconfigurable RF circuits. To that end, this research introduces several CMOS-integrated, transformer-based reconfigurable circuit techniques whose effectiveness is validated through measurements of designed transceiver front-end low-noise (LNA) and power amplifier (PA) prototypes. In the first part, the use of high figure-of-merit phase-change (PC) based RF switches in the reconfiguration of CMOS LNAs in the receiver front-end is proposed. The first reported demonstration of an integrated, PC-switch based, dual-band (3/5 GHz) reconfigurable CMOS LNA with transformer source degeneration and designed in a 0.13 μm process is presented. In the second part, a frequency-reconfigurable CMOS transformer combiner is introduced that can be reconfigured to have similar efficiencies at widely separated frequency bands. A 65-nm CMOS triple-band (2.5/3/3.5 GHz) PA employing the reconfigurable combiner was designed. In the final part of this work, the use of transformer coupled-resonators in mm-wave LNA designs for 28 GHz bands was investigated. To cover contiguous and/or widely-separated narrowband channels of the emerging 5G standards, a 65-nm CMOS 24.9-32.7 GHz wideband multi-mode LNA using one-port transformer coupled-resonators was designed. Finally, a 25.1-27.6 GHz tunable-narrowband digitally-calibrated merged LNA-vector modulator design employing transformer coupled-resonators is presented that proposes a compact, differential quadrature generation scheme for phased-array architectures.

Thesis (MTech (Electrical Engineering)--Cape Peninsula University of Technology, 2011 / Modern technologies have led to extensive digital music reproduction and distribution. It is fitting then that digital audio be amplified directly from its source rather than being converted to an analogue waveform before amplification. The benefits of using a digital controller for audio processing include being able to easily reconfigure the system and to add additional functions at a later stage. Digital audio is primarily stored as Pulse Code Modulation (PCM) while Pulse Width Modulation (PWM) is the most popular scheme used to drive a class-D amplifier. The class-D amplifier is selected in many applications due to its very high energy efficiency. Conventional PCM to PWM conversion is inherently nonlinear. Various interpolation schemes are presented in this research project which help to address the nonlinearity. Digitally generated PWM has a limited resolution which is constrained by the system clock. This thesis presents noise shaping techniques which increase the effective resolution of the PWM process without having to use an excessively high system clock. Noise shaping allows a low resolution modulator to be used to reproduce high resolution audio.

Electro-Magnetic Interference(EMI) degrades the perfomance of electronic systems. So, Amplifiers which are the basic building blocks used in the front-end of analog and mixed-signal Integrated Circuits (ICs) must be evaluated for EMI. This work introduces the most intriguing figure of merit, Electro-Magnetic Interference Rejection Ratio (EMIRR) to measure the EMI immunity of precision Instrumentation Amplifiers (INAs) that helps to select the EMI robust INAs for EMI critical applications. In this work, a new EMIRR measurement setup is implemented to measure the immunity of INAs for conducted EMI ranging from 10 MHz to 3 GHz. The shift in the DC offset voltage generated at the output of the INA due to RF rectification, is used to compute EMIRR. As part of the setup, the hardware evaluation board is designed and an automation test software is developed to run EMIRR measurements. Furthermore, EMIRR measurements are performed on several INAs with different specifications to compare and rank them on their EMI immunity levels. Additionally, with the help of EMIRR metric, suitable INAs for developing EMI-sensitive applications are proposed. Finally, the influence of amplifier bandwidth, the input capacitance, 50 Ω termination at the end of RF input trace, INA package parasitics and EMI filter bandwidth on EMIRR is analyzed with the measurement results.

This manuscript describes the design, development, and implementation of a linear high efficiency power amplifier. The symmetrical Doherty power amplifier utilizes TriQuint's 2nd Generation Gallium Nitride (GaN) on Silicon Carbide (SiC) High Electron Mobility Transistor (HEMT) devices (T1G6001032-SM) for a specified design frequency of 3.6 GHz and saturated output power of 40 dBm. Advanced Design Systems (ADS) simulation software, in conjunction with Modelithic's active and passive device models, were used during the design process and will be evaluated against the final measured results. The use of these device models demonstrate a successful first-pass design, putting less dependence on classical load pull analysis, thereby decreasing the design-cycle time. The Doherty power amplifier is a load modulated amplifier containing two individual amplifiers and a combiner network which provides an impedance inversion on the path between the two amplifiers. The carrier amplifier is biased for Class-AB operation and works as a conventional linear amplifier. The second amplifier is biased for Class-C operation, and acts as the peaking amplifier that turns on after a certain instantaneous power has been reached. When this power transition is met the carrier amplifier's drain voltage is already approaching saturation. If the input power is further increased, the peaking amplifier modulates the load seen by the carrier amplifier, such that the output power can increase while maintaining a constant drain voltage on the carrier amplifier. The Doherty power amplifier can improve the efficiency of a power amplifier when the input power is backed-off, making this architecture particularly attractive for high peak-to-average ratio (PAR) environments. The design presented in this manuscript is tuned to achieve maximum linearity at the compromise of the 6dB back-off efficiency in order to maintain a carrier-to- intermodulation ratio greater than 30 dB under a two-tone intermodulation distortion test with 5 MHz tone spacing. Other key figures of merit (FOM) used to evaluate the performance of this design include the power added efficiency (PAE), transducer power gain, scattering parameters, and stability. The final design is tested with a 20 MHz LTE waveform without digital pre-distortion (DPD) to evaluate its linearity reported by its adjacent channel leakage ratio (ACLR). The dielectric substrate selected for this design is 15 mil Taconic RF35A2 and was selected based on its low losses and performance at microwave frequencies. The dielectric substrate and printed circuit board (PCB) design were also modeled using ADS simulation software, to accurately predict the performance of the Doherty power amplifier. The PCB layout was designed so that it can be mounted to an existing 4" x 4" aluminum heat sink to dissipate the heat generated by the transistors while the part is being driven. The performance of the 3.6 GHz symmetrical Doherty power amplifier was measured in the lab and reported a maximum PAE of 55.1%, and a PAE of 48.5% with the input power backed-off by 6dB. These measured results closely match those reported by design simulations and demonstrate the models' effectiveness for creating a first-pass functional design.

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