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Widely used design techniques for radio frequency power amplifiers yield results which are approximate; the initial design is usually refined by applying trial-and-error procedures in the laboratory. More accurate design techniques are complicated in their application and have not gained acceptance by practicing engineers. A new design technique for VHF linear power amplifiers using bipolar junction transistors is presented in this report. This design technique is simple in its application but yields accurate results. The design technique is based upon a transistor model which is simple enough to be useful for design, but which is sufficiently accurate to predict performance at high frequencies. Additionally, the model yields insight into many of the processes which take place within the typical RF power transistor. The fundamental aspect of the model is the inclusion of charge storage within the transistor base. This charge storage effect gives rise to a nearly sinusoidal collector current waveform, even in a transistor which ostensibly is biased for class B or nonsaturating class C operation. Methods of predicting transistor input and output impedances are presented. A number of other topics related to power amplifier measurement and design are also included. A unique measurement approach which is ideally suited for use with power amplifiers is discussed. This measurement approach is a hybrid of the common S-parameter measurement technique and the "load-pull" procedure. Practical considerations such as amplifier stability, bias network design, and matching network topology are also included in the report. / Ph. D.

The objective of this research is to analyze and improve linearity of envelope elimination and restoration (EER) radio frequency (RF) power amplifiers. Envelope elimination and restoration was compared to other efficiency enhancement techniques and determined to likely be the most suitable solution for implementation of multimode, multiband portable RF transmitters. Distortion, stemming from dynamic power-supply modulation of RF transistors in EER RF power amplifiers was identified as one of the key challenges to the development of commercially viable EER transmitters. This dissertation presents a study of phase distortion in RF power amplifiers (PAs) with emphasis on identification of the origins of phase distortion in EER RF power amplifiers. Circuit-level techniques for distortion mitigation are also presented. Memory effects in conventional power amplifiers are investigated through the accurate measurement and analysis of phase asymmetry of out-of-band distortion components. Novel physically-based power amplifier model is developed for attributing measured memory effects to their physical origin. The amount of linearity correction, obtained through pre-distortion for a particular RF power amplifier, is then correlated to the behavior of the memory effects in the corresponding PA. Heterojunction field-effect transistor and heterojunction bipolar transistor amplifiers are used for investigation of voltage-dependent phase distortion in handset EER RF PAs. The distortion is found to stem from vector addition of signals, generated in nonlinear circuit elements of the PA. Specifically, nonlinear base-collector capacitance and downconversion of distortion components from second harmonic frequency are found to be the dominant sources of phase distortion. Shorting of second harmonic is proposed as a way to reduce the distortion contribution of the downconverted signal. Phase distortion is reduced by 50%, however a slight degradation in the amplitude distortion is observed. Push-pull architecture is proposed for EER RF power amplifiers to cancel distortion components, generated in the nonlinear base-collector capacitance. Push-pull implementation enables a 67% reduction in phase distortion, accompanied by a 1-2 dB reduction in amplitude distortion in EER RF power amplifiers. This work, combined with other studies in the field, will help advance the development of multimode, multiband portable RF transmitters, based on the envelope elimination and restoration architecture.

The objective of this research is to develop, characterize, and demonstrate novel parametric architectures capable of wideband operation while maintaining high gain and stability. To begin the study, phase-incoherent upconverting parametric amplifiers will be explored by first developing a set of analytical models describing their achievable gain and efficiency. These models will provide a set of design tools to optimize and evaluate prototype circuit boards. The prototype boards will then be used to demonstrate their achievable gain, bandwidth, efficiency, and stability. Further investigation of the analytical models and data collected from the prototype boards will conclude bandwidth and gain limitations and end the investigation into phase-incoherent upconverting parametric amplifiers in lieu of negative-resistance parametric amplifiers. Traditionally, there were two versions of negative-resistance parametric amplifiers available: degenerate and non-degenerate. Both modes of operation are considered single-frequency amplifiers because both the input and output frequencies occur at the source frequency. Degenerate parametric amplifiers offer more power gain than their non-degenerate counterpart and do not require additional circuitry for idler currents. As a result, a phase-coherent degenerate parametric amplifier printed circuit board prototype will be built to investigate achievable gain, bandwidth, and stability. Analytical models will be developed to describe the gain and efficiency of phase-coherent degenerate parametric amplifiers. The presence of a negative resistance suggests the possibility of instability under certain operating conditions, therefore, an in-depth stability study of phase-coherent degenerate parametric amplifiers will be performed. The observation of upconversion gain in phase-coherent degenerate parametric amplifiers will spark investigation into a previously unknown parametric architecture: phase-coherent upconverting parametric amplifiers. Using the phase-coherent degenerate parametric amplifier prototype board, stable phase-coherent upconversion with gain will be demonstrated from the source input frequency to its third harmonic. An analytical model describing the large-signal transducer gain of phase-coherent upconverting parametric amplifiers from the first to the third harmonic of the source input will be derived and validated using the prototype board and simulations.

Kwok Pui-ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves [79]-85). / Abstracts in English and Chinese. / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter CHAPTER 2 --- NONLINEAR BEHAVIOR OF RF POWER AMPLIFIERS --- p.5 / Chapter 2.1 --- Single Tone Excitation --- p.6 / Chapter 2.1.1 --- AM-AM Conversion --- p.7 / Chapter 2.1.2 --- AM-PM Conversion --- p.9 / Chapter 2.2 --- Two-Tone Excitation --- p.11 / Chapter 2.2.1 --- Intermodulation Distortion --- p.12 / Chapter 2.3 --- Digitally Modulated Signal Excitation --- p.13 / Chapter 2.3.1 --- Spectral Regeneration --- p.14 / Chapter 2.3.2 --- Adjacent Channel Power Ratio (ACPR) --- p.16 / Chapter CHAPTER 3 --- LINEARIZATION TECHNIQUES --- p.18 / Chapter 3.1 --- pre-distortion --- p.20 / Chapter 3.2 --- Feed-forward Techniques --- p.23 / Chapter 3.3 --- Harmonics Control Techniques --- p.24 / Chapter CHAPTER 4 --- SPECTRAL REGROWTH ANALYSIS USING VOLTERRA SERIES METHOD --- p.26 / Chapter 4.1 --- Introduction To Volterra Series Analysis --- p.27 / Chapter 4.1.1 --- Linear and Nonlinear Systems --- p.27 / Chapter 4.1.2 --- Evaluation of Volterra transfer function --- p.29 / Chapter 4.1.3 --- Volterra Series Analysis of Spectral Regrowth --- p.31 / Chapter 4.2 --- Nonlinear Model of GaAs MESFET Device --- p.33 / Chapter 4.3 --- Evaluation Of Nonlinear Responses --- p.35 / Chapter 4.3.1 --- First-Order Response --- p.36 / Chapter 4.3.2 --- Second-Order Response --- p.38 / Chapter 4.3.3 --- Third-Order Response --- p.39 / Chapter CHAPTER 5 --- EFFECT OF HARMONIC TUNING ON SPECTRAL REGROWTH --- p.42 / Chapter 5.1 --- Simulation of Digitally Modulated Signal --- p.43 / Chapter 5.2 --- Effect of Source Second Harmonic Termination --- p.44 / Chapter CHAPTER 6 --- EXPERIMENTAL VERIFICATION --- p.48 / Chapter 6.1 --- Circuit Design and Construction --- p.49 / Chapter 6.2 --- Setup and Measurement --- p.55 / Chapter 6.3 --- Experimental Results --- p.56 / Chapter 6.3.1 --- Small Signal Measurement --- p.56 / Chapter 6.3.2 --- Single Tone Characterization --- p.57 / Chapter 6.3.3 --- Two-Tone Characterization --- p.59 / Chapter 6.3.4 --- ACPR Characterization --- p.60 / Chapter 6.4 --- Comparison of Measurement and Simulation --- p.66 / Chapter CHAPTER 7 --- NONLINEAR TRANSCONDUCTANCE COEFFICIENTS EXTRACTION --- p.68 / Chapter 7.1 --- Large Signal Model --- p.69 / Chapter 7.2 --- Extraction of Nonlinear Transconductance --- p.71 / Chapter 7.2.1 --- Extraction of g1 --- p.71 / Chapter 7.2.2 --- Extraction of g2 and g3 --- p.72 / Chapter CHAPTER 8 --- CONCLUSION --- p.76 / FUTURE WORK RECOMMENDATION --- p.78 / REFERENCE

With the explosive growth of the wireless market, the demand for low-cost and highly-integrated radio frequency (RF) transceiver has been increased. Keeping up with this trend, complimentary metal-oxide-semiconductor (CMOS) has been spotlighted by virtue of its superior characteristics. However, there are challenges in achieving this goal, especially designing the transmitter portion. The objective of this research is to demonstrate the feasibility of fully integrated CMOS transmitter module which includes power amplifier (PA) and transmit/receive (T/R) switch by compensating for the intrinsic drawbacks of CMOS technology. As an effort to overcome the challenges, the high-power handling T/R switches are introduced as the first part of this dissertation. The proposed differential switch topology and feed-forward capacitor helps reducing the voltage stress over the switch devices, enabling a linear power transmission. With the high-power T/R switches, a new transmitter front-end topology - differential PA and T/R switch topology with the multi-section PA output matching network - is also proposed. The multi-stage PA output matching network assists to relieve the voltage stress over the switch device even more, by providing a low switch operating impedance. By analyzing the power performance and efficiency of entire transmitter module, design methodology for the high-power handling and efficient transmitter module is established. Finally, the research in this dissertation provides low-cost, high-power handling, and efficient CMOS RF transmitter module for wireless applications.

Energy-efficient radio frequency (RF) power amplifiers (PAs) are critical and paramount to achieve longer battery life in state-of-the-art portable systems because they typically determine and dominate the power consumption of such devices. In this dissertation, a high-efficiency, linear RF PA with a dynamically adaptive supply and bias current control for code division multiple access (CDMA) and wideband CDMA (WCDMA) is conceived, simulated, and experimentally demonstrated with a discrete PCB-level design and in integrated circuit (IC) form. The PA efficiency is improved by dynamically adjusting both its supply voltage and bias current, there by minimizing its quiescent power dissipation. The PA supply voltage is derived from the battery by a noninverting, synchronous buck-boost switching regulator because of its flexible functionality and high efficiency. Adjusting the PA supply voltage and bias current by tracking the output power, instead of following the complete envelope in large baseband bandwidth wireless applications, is achieved by a converter with a lower switching frequency and consequently higher light-load efficiency, which translates to prolonged battery life. A discrete PCB-level prototype of the proposed system with 915 MHz center frequency, CDMA IS-95 signal having 27-dBm peak-output power resulted in more than four times improvement in the average efficiency compared to a fixed-supply class-AB PA while meeting the required performance specifications. In the IC solution fabricated in AMIs 0.5-micron CMOS process through MOSIS, a dual-mode, buck-boost converter with pulse-width modulation (PWM) control for high power and pulse-frequency modulation (PFM) for low power is designed and implemented to improve the PA efficiency during active and standby operation, respectively. The performance of the dynamically adaptive supply and bias control IC was validated by realizing a 25-dBm, 1.96 GHz center frequency, WCDMA PA over an input supply range of 1.4 4.2 V. The PA with dual-mode power supply and bias control IC showed an average-efficiency improvement of seven times compared to a fixed-supply class-AB PA, which translates to five times improvement in battery life assuming the PA is active for 2 % of the total time and in standby mode otherwise.

Thesis (Ph. D.)--Ohio State University, 2007. / Full text release at OhioLINK's ETD Center delayed at author's request

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 112-118). Also available in electronic format on the Internet.

Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.