abstract: ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work presents `A 12 bit 25MSPS 1.2V pipelined ADC using split CLS technique' in IBM 130nm 8HP process using only CMOS devices for the application of Large Hadron Collider (LHC). CLS technique relaxes the gain requirement of op-amp and improves the signal-to-noise ratio without increase in power or input sampling capacitor with rail-to-rail swing. An op-amp sharing technique has been incorporated with split CLS technique which decreases the number of op-amps and hence the power further. Entire pipelined converter has been implemented as six 2.5 bit RSD stages and hence decreases the latency associated with the pipelined architecture - one of the main requirements for LHC along with the power requirement. Two different OTAs have been designed to use in the split-CLS technique. Bootstrap switches and pass gate switches are used in the circuit along with a low power dynamic kick-back compensated comparator. / Dissertation/Thesis / M.S. Electrical Engineering 2012

The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital alternatives. Thus, analog-to-digital converters (ADCs), as the interfaces between the analog world and the digital one, are driven to enhance their performance in terms of speed, resolution and power efficiency. However, in the presence of imperfections of device mismatch, thermal noise and reduced voltage headroom, efficient ADC design demands new strategies for design, calibration and optimization. Among various ADC architectures, successive-approximation-register (SAR) ADCs have received renewed interest from the design community due to their low hardware complexity and scaling-friendly property. However, the conventional SAR architecture has many limitations for high-speed, high-resolution applications. Many modified SAR architectures and hybrid SAR architectures have been reported to break the inherent constraints in the conventional SAR architecture. Loop-unrolled (LU) SAR ADCs have been recognized as a promising architecture for high-speed applications. However, mismatched comparator offsets introduce input-level dependent errors to the conversion result, which deteriorates the linearity and limits the resolution and the resolution of most reported SAR ADCs of this kind are limited to 6 bits. Also, for high-resolution SAR ADCs, the comparator noise specification is very stringent, which imposes a limitation on ADC speed and power-efficiency. Lastly, capacitor mismatch is an important limiting factor for SAR ADC linearity, and generally requires dedicated calibration to achieve efficient designs in terms of power and area. In this work, we investigate the impacts of offset mismatch, comparator noise and capacitor mismatch on high-speed SAR ADCs. An analytical model is proposed to estimate the resolution and predict the yield of LU-SAR ADCs with presence of comparator offset mismatch. A background calibration technique is proposed for resolving the comparator mismatch issue. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7-dB to 42.9-dB. The ADC consumes 640 μW from a 1.2 V supply with a Figure-of-Merit (FoM) of 37.5-fJ/conv-step. Moreover, the bit-wise impact of comparator noise is studied for LU-SAR ADCs. Lastly, an extended statistical element selection (SES) calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. Based on these techniques, a high-resolution, asynchronous SAR architecture employing multiple comparators with different speed and noise specifications to optimize speed and power efficiency. A 12-bit prototype ADC is fabricated in a 1P9M 65nm CMOS technology, and fits into an active area of 500 μm × 200 μm. At 125 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 64.4 dB and a spurious-free-dynamic-range (SFDR) of 75.1 dB at the Nyquist input frequency while consuming 1.7 mW from a 1.2 V supply. The resultant figure-of-merit (FoM) is 10.3 fJ/conv-step.

The aim of this dissertation was the design, implementation and performance evaluation of a Recursive Least Squares (RLS), lattice based, adaptive, multidimensional, decision feedback equaliser (DFE) for the spectrally efficient four-dimensional digital modulation technique, re¬ferred to as Quadrature-Quadrature Phase-Shift Keying, Q2pSK. Q2PSK constitutes a relatively new modulation technique, and the application of adaptive equalisation to this technique has not yet been considered in the open literature. This dissertation represents an in depth study into the Q2PSK modulation technique, as well as the optimal implementation, in simulation, of such a modem to aid the inclusion of the adap¬tive lattice DFE, for application to high speed mobile digital communication over the V /UHF channel in the presence of multi path propagation. Specific aspects of synchronization applicable to this modem platform are also addressed. An in depth study was also conducted into the realisation of a V /UHF channel simulation, capable of producing a Ricean and/or Rayleigh fad¬ing multipath propagation environment for the evaluation of the modem platform and adaptive equaliser structure. The theoretical analysis of the effect of multi path on a Q2PSK signal led to the correct design of the adaptive lattice structure, as well as the correct interfacing of the equaliser to the receiver platform. The performance of the proposed synchronisation strategies, in tandem with the equalisation technique were evaluated for several static, as well as fading multipath channels. The simulation results obtained show the equaliser operates correctly, and can give large performance gains over the static matched filter (matched to the transmitted waveform) implementation of the modem platform. Several simulations were specifically designed to highlight the performance limitations of the adaptive equalisation technique. / Dissertation (MEng (Digital Communication))--University of Pretoria, 2006. / Electrical, Electronic and Computer Engineering / unrestricted

No description available.

No description available.

No description available.

Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the approaches discussed here are independent of architecture; some solutions take advantage of specific architectures. Chapter 1 provides the problem formulation and reviews the errors found in ADCs as well as a brief literature review of available TI-ADC error correction solutions. Chapter 2 presents the methods and materials used in implementation as well as extend the state of the art for post conversion correction. Chapter 3 presents the simulation results of this work and Chapter 4 concludes the work. The contribution of this research is three fold: A new behavioral model was developed in SimulinkTM and MATLABTM to model and test linear and nonlinear mismatch errors emulating the performance data of actual converters. The details of this model are presented as well as the results of cumulant statistical calculations of the mismatch errors which is followed by the detailed explanation and performance evaluation of the extension developed in this research effort. Leading post conversion correction methods are presented and an extension with derivations is presented. It is shown that the data converter subsystem architecture developed is capable of realizing better performance of those currently reported in the literature while having a more efficient implementation.

No description available.

This paper demonstrates conversion of an analog filter into a digital filter using computer aided software. The filter design to be demonstrated is a common third order Butterworth filter. This paper is not an attempt to review all filter designs or applications, but rather the attempt is to give a detailed explanation of the steps required to design almost any digital filter. No knowledge of the Intel Series 210 microcomputer development system is assumed. The appendices contain introduction to the Series 210 system. Chapter I demonstrates the steps needed to design this filter without computer aid. Included are both analog and digital filter response characteristics. Chapter II supplemented with Appendix C demonstrates the computer aided filter design. Again, filter characteristics are included. Chapter III compares the results of Chapter I and II. Even though this paper attempts to be inclusive of most of the computer details, it should not be used in exclusion of the available Series 210 manuals.

In many developing countries health care conditions are poor and there is a lack of healthcare professionals and diagnostics tools. Cheap and easy-to-use diagnostics tools have been developed to make practicing medicine easier under these conditions. However, signal monitors can be many and spread out, making it hard for the limited number of medical workers to handle. The monitors are also stationary, making mobile supervision impossible. In this thesis a solution is suggested, made of a hardware setup consisting of an Arduino UNO and Bluetooth module paired with an application, capable of analog to digital conversion, wireless transfer and display of medical signals. Furthermore, two different QRS detection algorithms are tested, a larger and accurate model called Pan-Tompkins and a smaller and faster, moving average based filtering system. The transmission circuit as well as the signal displayed showed promise. However, the analog to digital conversion was noisy due to the power source. The tested algorithms showed that speed and low computational requirements are traded for precision.