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This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the inherent delay originated from the DCT adder will cause instability to the modulator and complex additional branches are usually needed to stabilize the loop. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the instability issue is therefore solved. Another proposed low-power design technique is to feed differentiated inverted quantization noise to the input of the last integrator. The modulator noise-shaping order with this proposed technique is effectively increased from two to three without adding additional active elements. The delta-sigma ADC with the proposed architectural design techniques has been implemented in transistor-level and fabricated in 0.18 µm CMOS technology. Measurement results showed a SNDR of 99.3 dB, a DR of 101.3 dB and a SFDR of 112 dB over 20 kHz signal bandwidth, resulting in a very low figure-of-merit (FoM) in its application category. Finally, two new circuit ideas, low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs and switched-resistor tuning technique for highly linear Gm-C filter design are presented. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 9, 2012 - June 9, 2014

Multiple-input multiple-output (MIMO) radars, which utilize multiple transmitters and receivers to send and receive independent waveforms, have been actively investigated as a next generation radar technology inspired by MIMO techniques in communication theory. Complementary metal-oxide-semiconductor (CMOS) technology offers an opportunity for dramatic cost and size reduction for a MIMO array. However, the resulting formidable signal processing burden has not been addressed properly and remains a challenge. On the other hand, from a block-level point of view, an analog-to-digital converter (ADC) is required for mixed-signal processing to convert analog signals to digital signals, but an ADC occupies a significant portion of a system's budget. Therefore, improvement of an ADC will greatly enhance various trade-offs. This research presents an alternative and viable approach for a MIMO array from a system architecture point of view, and also develops circuit level improvement techniques for an ADC. This dissertation presents a fully-integrated analog pulse compressor (APC) based on an analog matched filter in a mixed signal domain as a key block for the waveform diversity MIMO radar. The performance gain of the proposed system is mathematically presented, and the proposed system is successfully implemented and demonstrated from the block level to the system level using various waveforms. Various figures of merit are proposed to aid system evaluations. This dissertation also presents a low-power ADC based on an asynchronous sample-and-hold multiplying SAR (ASHMSAR) with an enhanced input range dynamic comparator as a key element of a future system. Overall, with the new ADC, a high level of system performance without severe penalty on power consumption is expected. The research in this dissertation provides low-cost and low-power MIMO solutions for a future system by addressing both system issues and circuit issues comprehensively.

Typescript (photocopy). / Digitized by Kansas State University Libraries / Department: Electrical and Computer Engineering.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The Precision Fires Rocket and Missile Systems (PFRMS) Program Office continually undertakes Stockpile Reliability Testing (SRP) to ensure the validity of the accumulated weapons and increase the she lf life of these weapon systems. MLRS is a legacy weapon system that has been undergoing SRP testing for over 20 years. The PFRMS Program Office has a need for a miniature Tactical Telemetry System that will monitor the fuze performance of the MLRS Rocket during SRP testing. This paper will address a technical approach of how a small Tactical Telemetry System could be built to meet this requirement. The Tactical Telemetry system proposed in this paper will monitor fuze functions, operate across the wide environmental spectrum of the SRP tests, and physically fit in the nose area without altering the overall tactical rocket appearance or operation.

The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate.

by Leung Sze-wing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (leaves 79-84). / Abstracts in English and Chinese. / ACKNOWLEDGEMENT --- p.II / ABSTRACT --- p.III / 摘要 --- p.V / CONTENTS --- p.VI / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Objectives --- p.1 / Chapter 1.2 --- Prevalence of Heart Diseases --- p.1 / Chapter 1.3 --- Importance of ECG Monitoring --- p.2 / Chapter 1.4 --- Wireless Electrode --- p.2 / Chapter 1.5 --- Analogue-to-Digital Converters --- p.3 / Chapter 1.6 --- Organization of Thesis --- p.4 / Chapter CHAPTER 2 --- LITERATURE REVIEW --- p.5 / Chapter 2.1 --- Telemetry --- p.5 / Chapter 2.1.1 --- "Definitions of ""Telemetry “" --- p.5 / Chapter 2.1.2 --- Advantages of Telemetry --- p.6 / Chapter 2.1.3 --- History of Telemetry --- p.7 / Chapter 2.1.4 --- Special Considerations on Telemetry System --- p.10 / Chapter 2.2 --- Sigma-Delta Converter --- p.12 / Chapter 2.2.1 --- Conventional Digitizing Circuitry --- p.12 / Chapter 2.2.2 --- "Single, Dual-Slope A/D Converters" --- p.13 / Single-Slope A/D Converter --- p.13 / Dual-Slope Converter --- p.75 / Chapter 2.2.3 --- Successive Approximation (SAR) --- p.17 / Chapter 2.2.4 --- Flash Converters --- p.18 / Chapter 2.2.5 --- Sigma-Delta Converter --- p.18 / Chapter 2.3 --- Conclusion --- p.20 / Chapter CHAPTER 3 --- WIRELESS ELECTRODE --- p.21 / Chapter 3.1 --- """Single Electrode"" Measurement" --- p.21 / Chapter 3.2 --- VSE (Virtual Single Electrode) --- p.21 / Concentric Electrode --- p.21 / Chapter 3.3 --- WE (Wireless Electrode) --- p.24 / Chapter 3.4 --- Discussion --- p.29 / Chapter CHAPTER 4 --- SIGMA-DELTA CONVERTER FOR ECG SIGNALS --- p.30 / Chapter 4.1 --- Motivations --- p.30 / Chapter 4.2 --- Baseband Application --- p.31 / Chapter 4.2.1 --- Simulation Results --- p.31 / Chapter 4.2.2 --- Experimental Results --- p.48 / Chapter 4.3 --- Wireless Application --- p.58 / Chapter 4.3.1 --- General Description --- p.58 / Chapter 4.3.2 --- Simulation Results --- p.59 / Chapter 4.3.3 --- Scenario 1 (Analogue Decoding) --- p.70 / Chapter 4.3.4 --- Scenario II (Digital Decoding) --- p.73 / Chapter 4.4 --- Discussion and Conclusion --- p.76 / Chapter CHAPTER 5 --- CONCLUSION AND FUTURE WORK --- p.77 / Chapter 5.1 --- General Conclus ion --- p.77 / Chapter 5.2 --- Future Work --- p.78 / BIBLIOGRAPHY --- p.79 / LIST OF ABBREVIATIONS --- p.85

Scaling of CMOS to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower VDD supply voltage and decreased power consumption for logic functions. However, most traditionally prevalent ADC architectures are not well suited to the lower VDD environment. The improvement in time resolution enabled by increased digital speeds naturally drives design toward time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The major obstacle in the VCO-based technique is linearizing the VCO voltage-to-frequency characteristic. Achieving signal-to-noise (SNR) performance better than -40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. A further challenge is implementing calibration without degrading energy efficiency performance. This thesis project discusses a complete design of a 10 bit three stage ring VCO-based ADC. A lookup-table (LUT) digital correction technique enabled by the "Split ADC" calibration approach is presented suitable for linearization of the ADC. An improvement in the calibration algorithm is introduced to ensure LUT continuity. Measured results for a 10 bit 48.8-kSps ADC show INL improvement of 10X after calibration convergence.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1980. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographcial references. / by Helen Louise Graham. / M.S.

Ko, Chi Tung. / On t.p. "delta" and "sigma" appear as the Greek letters. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.1 / 摘要 --- p.3 / Acknowledgements --- p.4 / Table of Contents --- p.5 / List of Figures --- p.8 / List of Tables --- p.13 / Chapter Chapter 1 --- Introduction --- p.14 / Chapter 1.1 --- Motivation --- p.14 / Chapter 1.2 --- Objectives --- p.17 / Chapter 1.3 --- Organization of the Thesis --- p.17 / References --- p.18 / Chapter Chapter 2 --- Fundamentals of Delta-sigma Modulators --- p.20 / Chapter 2.1 --- Delta-sigma Modulator as a Feedback System --- p.20 / Chapter 2.2 --- Quantization Noise --- p.22 / Chapter 2.3 --- Oversampling --- p.23 / Chapter 2.4 --- Noise Shaping --- p.25 / Chapter 2.5 --- Performance Parameters --- p.27 / Chapter 2.6 --- Baseband Modulators vs Bandpass Modulators --- p.27 / Chapter 2.7 --- Discrete-time Modulators vs Continuous-time Modulators --- p.28 / Chapter 2.8 --- Single-bit Modulators vs Multi-bit Modulators --- p.29 / Chapter 2.9 --- Non-linearity and Image Problems in Multi-bit Delta-sigma Modulators --- p.29 / Chapter 2.9.1 --- Non-linearity Problem --- p.29 / Chapter 2.9.2 --- Image Problem --- p.31 / Reference --- p.36 / Chapter Chapter 3 --- Image Rejection and Non-linearity Suppression Techniques for Quadrature Multi-bit Δ¡♭ Modulators --- p.38 / Chapter 3.1 --- Quadrature DEM Technique --- p.38 / Chapter 3.1.1 --- Introduction and Working Principle --- p.38 / Chapter 3.1.2 --- Behavioral Simulation Results --- p.42 / Chapter 3.2 --- IQ DWA Technique --- p.44 / Chapter 3.2.1 --- Introduction and Working Principle --- p.44 / Chapter 3.2.2 --- Behavioral Simulation Results --- p.49 / Chapter 3.3 --- DWA and Bit-wise Data-Dependent DEM --- p.52 / Chapter 3.3.1 --- Introduction and Working Principle --- p.52 / Chapter 3.3.2 --- Behavioral Simulation Results --- p.54 / Chapter 3.4 --- Image Rejection Technique for Quadrature Mixer --- p.61 / Chapter 3.5 --- Conclusion --- p.63 / Reference --- p.64 / Chapter Chapter 4 --- System Design of a Multi-Bit CT Modulator for GSM/WCDMA Application --- p.65 / Chapter 4.1 --- Objective of Design and Design Specification --- p.65 / Chapter 4.2 --- Topology Selection --- p.65 / Chapter 4.3 --- Discrete-time Noise Transfer Function Generation --- p.66 / Chapter 4.4 --- Continuous-time Loop Filter Transfer Function Generation --- p.69 / Chapter 4.5 --- Behavioral Model of Modulator --- p.69 / Chapter 4.6 --- Dynamic Range Scaling --- p.75 / Chapter 4.7 --- Behavioral Modeling of Operational Amplifiers --- p.77 / Chapter 4.8 --- Impact of RC Variation on Performance --- p.85 / Chapter 4.9 --- Loop Filter Component Values --- p.88 / Chapter 4.10 --- Summary --- p.90 / Reference --- p.90 / Chapter Chapter 5 --- Transistor-level Implementation of Modulators --- p.92 / Chapter 5.1 --- Overview of Design --- p.92 / Chapter 5.2 --- Design of Operational Transconductance Amplifiers (OTAs) --- p.94 / Chapter 5.2.1 --- First Stage --- p.94 / Chapter 5.2.2 --- Second and Third Stages --- p.98 / Chapter 5.3 --- Design of Feed-forward Transconductance (Gm) Cells --- p.101 / Chapter 5.4 --- Design of Quantizer --- p.102 / Chapter 5.4.1 --- Reference Ladder Design --- p.102 / Chapter 5.4.2 --- Comparator Design --- p.104 / Chapter 5.5 --- Design of Feedback Digital-to-Analog Converter (DAC) --- p.106 / Chapter 5.5.1 --- DWA and DEM Logic --- p.107 / Chapter 5.5.2 --- DAC Circuit --- p.109 / Chapter 5.6 --- Design of Integrated Mixers --- p.111 / Chapter 5.7 --- Design of Clock Generators --- p.112 / Chapter 5.7.1 --- Master Clock Generator --- p.112 / Chapter 5.7.2 --- LO Clock Generator --- p.114 / Chapter 5.7.3 --- Simulation Results --- p.116 / Reference --- p.125 / Chapter Chapter 6 --- Physical Design of Modulators --- p.127 / Chapter 6.1 --- Floor Planning of Modulator --- p.127 / Chapter 6.2 --- Shielding of Sensitive Signals --- p.130 / Chapter 6.3 --- Common Centroid Layout --- p.130 / Chapter 6.4 --- Amplifier Layout --- p.132 / Reference --- p.137 / Chapter Chapter 7 --- Conclusions --- p.138 / Chapter 7.1 --- Conclusions --- p.138 / Chapter 7.2 --- Future Works --- p.138 / Appendix A Schematics of Building Blocks --- p.140 / First Stage Operational Amplifier --- p.140 / First Stage Amplifier Local Bias Circuit --- p.140 / Second and Third Stage Operational Amplifier --- p.141 / Second and Third Stage Local Bias Circuit --- p.141 / CMFB Circuit (First Stage) --- p.142 / CMFB Circuit (Second Stage) --- p.142 / Gm-Feed-forward Cells --- p.143 / Gm Feed-forward Cell Bias Circuit --- p.143 / Reference Ladder Circuit --- p.144 / Pre-amplifier Circuit --- p.145 / Latch Circuit --- p.145 / DAC Circuit (Unit Cell) --- p.146 / Author's Publications --- p.147