This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.

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Thesis (M. A.) --University of Limpopo, 2021 / This is an exploratory study conducted to assess the effectiveness of the digital migration in South Africa. This study focused on two areas of domicile, which embarked on the process of migrating in Limpopo Province i.e. Shayandima Village in Thohoyandou and Rapotokwane Village in Bela-Bela. The theories that were used to guide the study were the diffusion of innovations theory, political economic theory and media policy theory. These theories were employed to assist in assessing the process, the effectiveness and the importance of Digital Migration. The results for this study are revealed that 85% of respondents asserted that digital broadcasting is very effective and easy to use compared to the analog broadcasting systems, as it shows clear pictures, quality sound and access to more television channels. This help television viewers to get quality television programs. It was interesting to note that respondents mentioned that they did not regret migrating from analog to digital broadcasting because of the benefits and impact that the Set Top Boxes Set (STB)s have on their televisions. The findings reveal that the STBs are effective and affordable and enable to watch more television channels. There is also a need for the Department of Communication and Digital Technologies to ensure that every household in South Africa migrates to digital broadcasting system

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Telemetry & Instrumentation, in conjunction with NASA’s Kennedy Space Center, has developed a commercial, intelligent, data acquisition module that performs all functions associated with acquiring and digitizing a transducer measurement. These functions include transducer excitation, signal gain and anti-aliasing filtering, A/D conversion, linearization and digital filtering, and sample rate decimation. The functions are programmable and are set up from information stored in a local Transducer Electronic Data Sheet (TEDS). In addition, the module performs continuous self-calibration and self-test to maintain 0.01% accuracy over its entire operating temperature range for periods of one year without manual recalibration. The module operates in conjunction with a VME-based data acquisition system.

Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3.84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamique.

Cette thèse est le fruit d'un partenariat entre la BL TVFE de NXP Semiconductors et l'ESIEE dans le cadre d'une thèse CIFRE. Le but est d'apporter une solution qui permette la réception de plusieurs canaux pour le câble. Ce sujet est lié à la problématique de numérisation large bande. Dans la première partie, nous faisons un état-de-l'art sur les convertisseurs analogiques-numériques (CAN), sur les architectures parallèles (entrelacement temporel et bancs de filtres hybrides (BFH)), et sur les méthodes d'échantillonnage (passe-bande et complexe). Puis, nous étudions une architecture composée d'un banc de filtres analogiques et un banc de CANs. Nous cherchons à réduire surtout le taux d'échantillonnage. Nous comparons notre solution à un CAN large bande performant, avec notre fonction de coût. L'un des avantages de cette architecture est que tous les composants sont faisables, même les CANs, et qu'il est possible d'éteindre des sous-bandes pour diminuer la consommation. Cette solution est intéressante pour le moment mais n'est pas compétitive en termes de consommation et de surface. Nous proposons une alternative dans la partie 3, avec les BFH. Nous étudions cette architecture, en gardant à l'esprit la faisabilité de la solution. Nous avons choisi un BFH à deux voies, avec un filtre analogique passe-bas et un passe-haut. Puis, nous proposons un algorithme d'optimisation des filtres de synthèse pour atteindre nos objectifs de distorsion et de réjection de repliement. Une identification des filtres analogiques est aussi présentée. Finalement, une réalisation physique prouve le concept et valide les limitations théoriques de cette architecture / This thesis is a partnership between the BL TVFE of NXP Semiconductors and ESIEE. Its goal is to provide a solution to multi-channel reception for cable network. This is linked to the problematic of broadband digitization. In the first part, the state-of-the art of ADCs, parallel architectures (TI and HFB) and sampling methods (bandpass sampling and complex sampling) is recalled. Then we study an architecture called RFFB with a bank of analog filters and a bank of ADCs. We try to reduce the constraints on ADCs, especially the sampling rate with the different sampling. We propose an interesting solution to broadband digitization and compare this solution to a challenging wideband ADC, using the cost function we introduce. This architecture has the major advantage that all the components are feasible, even the ADCs, and it is possible to switch-off subbands to save power. It could be a good solution at the present time but it is not competitive in terms of power consumption and surface. An alternative is proposed in Part 3, where we study Hybrid Filter Banks. It is interesting to study this architecture with realization feasibility in mind. This is why we select a 2-channel HFB with a lowpass filter and a highpass filter as analog filters. Then we propose an efficient optimization algorithm to find the best synthesis filters and reach our targets of distortion and aliasing rejection. An identification of analog filters is also suggested to cope with the issue of sensitivity to analog errors. Finally, a physical realization proves the concept of aliasing rejection and confirms the theoretical issues of this architecture

Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues are extremely helpful for curing many neural injuries and cognitive diseases. One method to discover this field is by designing a chip embedded in brains with probes to actual neurons. It is obvious that batteries are not practical for these applications and thereby RF radiation is used as power sources, revealing that chips should operate under a very low power supply. Since neural signals are analog waveforms, analog-to-digital converter (A/D converter, ADC) is the key component in a neural recorder chip. This thesis proposes the complete design of a low power 8-bit successive approximation register (SAR) A/D converter for use in a wireless neural recorder chip, realizing the function of digitizing a sampled neural signal with a frequency distribution of 10Hz to 10kHz. A modified energy-saving capacitor array in the SAR structure is provided to help save power dissipation. Therefore, the ADC shall operate within a power budget of 20­μW maximum from a 1­V power source, at a clock frequency of 500kHz corresponding to a conversion rate of 55.5-kS/s. All the circuits are designed and implemented based on the IBM/Global Foundries 8HP 130nm BiCMOS technology. Simulations of schematic and layout versions are done respectively to verify the functionality, linearity and power consumption of the ADC. Key words: Successive approximation register analog-to-digital converter (SAR-ADC), low power design, energy-saving capacitor array, neural recorder applications

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois ambientes diferentes de radiação. O primeiro experimento considera um teste de dose total ionizante (Total Ioninzig Dose - TID) sob irradiação gama, e o segundo experimento considera os efeitos de eventos singulares (Single Event Effects - SEE) sob irradiação por íons pesados. O SAD é composto, principalmente, por três conversores analógicos-digitais (ADCs) e dois votadores. A técnica usada é a Redundância Modular Tripla (Triple Modular Redundancy - TMR), com implementação em diferentes níveis de diversidade (temporal e arquitetural). O sistema é construído em um System-on-Chip programável (PSoC 5LP) da Cypress Semiconductor, fabricado em tecnologia CMOS de 130nm. Para a irradiação com TID, se utiliza o PSoC de part number CY8CKIT-050 sob uma fonte de radiação gama de 60Co (cobalto-60), com uma taxa de dose efetiva de 1 krad(Si)/h por 10 dias, atingindo uma dose total de 242 krad(Si) Para SEE se utiliza o protótipo PSoC de part number CY8CKIT-059 (sem encapsulamento) em um acelerador de partículas 8UD Pelletron usando 16O (oxigeno-16) ao vácuo, com energia de 36 MeV em um LET aproximado de 5.5 MeV/mg/cm2 e uma penetração no silício de 25 mm, resultando em um fluxo de 354 p/cm2.s, e uma fluência de 5077915 p/cm2 depois de 14755 segundos (4h 09min). Observou-se com o resultado do primeiro estudo que um (1) dos módulos do sistema apresentou uma degradação significativa na sua linearidade durante a irradiação, enquanto os outros tiveram uma degradação menos grave, mantendo assim a funcionalidade e confiabilidade do sistema. Durante o tempo de irradiação do segundo estudo, foram observadas 139 falhas: 53 SEFIs (Single Events Funtional Interrupt), 29 falhas críticas e 57 falhas SDC (Silent Data Corruption), atingindo as diferentes copias do sistema e um dos votadores do mesmo, mas sempre mantendo a saída esperada. Nos dois experimentos se evidencia a vantagem de usar a diversidade de projeto, além do TMR, para melhorar a resiliência e confiabilidade em sistemas críticos redundantes que trabalham com sinais mistos. / This work presents an analog-to-digital data acquisition system (DAS) based on a redundant scheme with design diversity, being tested in two different radiation environments. The first experiment is a Total Ionizing Dose (TID) essay and the second one considers Single Event Effects (SEE) under heavy ion irradiation. The DAS is mainly composed of three analog-todigital converters (ADCs) and two voters. The used technique was the Triple Modular Redundancy (TMR) implementing different levels of diversity (temporal and architectural). The circuit was built in a programmable System-on-Chip (PSoC 5LP) from Cypress Semiconductor, fabricated in a 130nm CMOS technology process. For the irradiation with TID the part number CY8CKIT-050 PSoC was used under a 60Co (cobalt-60) gamma radiation source, with an effective dose rate of 1 krad(Si)/h during 10 days, reaching a total dose of 242 krad(Si). For SEE experiments the part number CY8CKIT-059 (without encapsulation) PSoC prototype under a 8UD Pelletron particle accelerator using 16O (oxigen-16) under vacuum, with an energy of 36 MeV, resulting in a flux of 354p/cm2.s and a fluence of 5077915p/cm2 after 14755 seconds (4h 09min). As result of the first study it was observed that one of the system’s modules presented a significant degradation in its linearity during the irradiation, while degradations in the other modules were not as deep, maintaining the system’s functionality and reliability. During the period of the radiation of the second study, 139 faults were observed, 82 of them were critical and 57 were SDC (Silent Data Corruption), reaching the different system copies and one of the voters, while always maintaining the correct output. The advantage of using diversity, besides TMR, to improve resilience and reliability in redundant systems working with mixed signals was demonstrated in both experiments.