While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels. The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme. A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations. A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs. / <p>QC 20150422</p>

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 143-145). Also available in electronic format on the Internet.

abstract: Several state of the art, monitoring and control systems, such as DC motor controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2014

This work deals with the collection of data from analog sensors, their storage and display using the Raspberry Pi microcomputer. In more detail it deals with selecting the appropriate analog-to-digital converter, selecting the appropriate storage and database server, web server and application to display the measured data.

The paper discusses a possibility of localization of a sound source inside a wooden beam. The method is based on measuring signals from two microphones, assuming the sound source lies between the microphones. The position of the sound source is calculated from the delay between the signals. The calculation of the delay is done by correlation of the signals in the frequency range. ARM architecture microcontroller is used to for the calculations.

The text is focused on development induction heating coltroller. The motivation to create such a device was to correct deficiencies and add the necessary functionality for a device of this type. This was achieved mainly by adding the graphic display and USB interface. Graphic TFT display with buttons and a rotary encoder creates user interface. Part of the control unit is also circuit evaluateing temperature from three thermocouples. The paper dealt with the optimal solution for power supply, communication between control unit and power part, way of controlling graphical TFT display and selection of other components. The core is of course, suitable microcontroller, which manage all parts of the device.

La tendance du secteur automobile à développer des capteurs etactionneurs intelligents, faire cohabiter l’électronique analogique et l’électroniquenumérique devient un art. Placé au sein des actionneurs, pour la sécurité et le confortdes passagers, les convertisseurs analogique-numérique (CAN) sont les composantsclés de ces systèmes intelligents. Un CAN rapide, précis, et peu cher serévèle être un précieux allié pour les équipementiers automobiles. Pour diminuerles coûts, et faciliter l’utilisation de ce bloc, la surface de silicium occupée doit êtreconsidérablement réduite à moins de 0.5mm2. Quant à la précision du convertisseur,12-bits tous les 5 coups d’une horloge de 100 MHz sont nécessaires pour unetempérature de -40°C à 175°C.Ce travail de recherche se focalise sur l’amélioration de l’efficacité énergétiquesous les contraintes que l’environnement automobile représente. Notre principalecontribution réside dans le développement par une approche top-downd’une nouvelle architecture à 3 étages de topologies différentes. Le premier étageest un ΣΔ-Incrémental intrinsèquement linéaire. Le second étage est un algorithmiquepour augmenter rapidement la résolution. Enfin, un SAR accroît la résolutionavec faible consommation de puissance et surface de silicium.Suite à l’analyse de 40 années d’état de l’art, la nouvelle architecture proposéefut validée par vérification des non-linéarités statiques (DNL, INL) à différentsniveaux de modélisation. Commençant par un modèle MATLAB sans leslimitations analogiques, le niveau de modélisation se raffine petit à petit jusqu’auniveau transistor du convertisseur. Un modèle Verilog-A permit la déterminationdes spécifications minimales des briques de base analogiques: les comparateurs etles amplificateurs à transconductance. La sensibilité de ces derniers à la températurefut analysée pour limiter les erreurs commises sur les tensions analogiques.Une fois dessinés et les parasites extraits, les modèles variant avec la températureremplacent leurmodèle Verilog-A respectif afin d’obtenir les performances finales.Parallèlement, deux architectures de comparateurs ont été évaluées en températureau sein d’une première puce de test. Deux méthodes ont été utilisées pour estimerl’offset des comparateurs, et un nouveau circuit asynchrone estime le délai.Une seconde puce de test permet de vérifier la sensibilité du SAR à la températuremalgré un fonctionnement pseudo-asynchrone.Pour les comparateurs, le nouveau circuit de mesure différentielle du retardmontre une précision de 60 ps dans le pire des cas, pour la plus petite surface surpuce connue en considérant la technologie utilisée. Comme la variation du retardest dépendante de la température, le choix d’un Strong-ARM (SA) ou d’un Double-Tail (DT) dépendra du bruit, de la puissance, de la tension d’alimentation, et de laspécification de kickback. Pour une tension d’alimentation standard, les SA comparateursciblent les systèmes à faible consommation avec une tolérance élevéepour le kickback différentiel. Au contraire, les DT comparateurs acceptent uneplage de tension d’alimentation plus faible, et présentent un faible kickback différentiel,mais un bruit plus important. Testé de -40°C à 200°C, le dernier étagedu CAN proposé, n’a pas besoin d’être calibré jusqu’à 180°C. Les résultats encourageantssur cet étage permettent la réutilisation de celui-ci pour calibrer les étagesprécédents. Et pour le CAN, nous estimons une résolution possible de 11,2 bitsen 5 cycles d’horloge par échantillon avec une extension à 13,3 bits en 6 cyclesd’horloge. La surface estimée est de 0,12mm2.La puce de test pour le CAN est en cours de finalisation, une première étapesera sa caractérisation. Les résultats de cette session de mesure détermineront s’ilest possible de pousser l’architecture à des fréquences plus élevées pour ensuitetirer parti du traitement numérique pour conserver les performances. / In the automotive industry, the trend being to develop smartsensors and actuators, the on-board electronic has been ever more an artful workto combine analog electronics and the digital one. While many monitoring andcontrol systems play a crucial role as well for the safety as for the comfort of passengers,small components, like ADCs, are mandatory as a building block or as anessential functionality integrated into smart actuators. To that extent, a low-cost,fast and accurate analog to digital converter operating in those harsh conditionsis a good ally for equipment manufacturers. To decrease the cost, the area is ofprimary concern. Considering re-use of the ADC as an IP-bloc, the area has beenlimited to less than half a square millimeter for an low-oversampling ratio of 5 tooutput a 12-bit code at a sample rate of 20 MSamples/s, over a wide temperaturerange from-40°C to 175°C.This work focuses on the design of high-precision, high-speed and energyefficient ADC under the harsh environment the automotive one represents. Ourmain contribution relies on the development of an new hybrid topology proposalusing 3 stages to cope with such constraints based on a top-down approach: A firstcounting stage inherently linear, an algorithmic stage allowing to increase rapidlythe precision, and a SAR stage, ideal in terms of area and consumption, for a lownumber of bits.Based on a 40 years literature review, a new topology proposal has been validatedby checking its static metric of non-linearity (DNL, INL) at different level ofmodelisation. Starting by a MATLAB implementation without analog limitations,we refined step by step the model tillwe reach a transistor level of the ADC. Thence,Verilog-A model allows us to fix the minimum requirements of the key analog buildingblocks, to wit comparators and OTA. The latter has been analysed in order tolimit the settling error sensitivity to the temperature. Laid-out, parasitic extractedsimulation results of these considering PVT variations, they replace then previoushigh-level model to give final performances. Meanwhile, two well-known comparatorarchitectures have been assessed as IP blocs inside a first test chip. To performthe offset extraction, both a conventional and a feedback loop have been inspected.To assess, the delay a new asynchronous circuit has been proposed. A secondchip tests the sensitivity of the SAR to validate both the pseudo-asynchronousdigital scheme, and a Double-Tail comparator in real operating conditions.For comparators, the new differential measurement circuit of the delaydemonstrate an accuracy of 60 ps in the worst case, over a large temperature rangefor the smallest chip area known with respect to the technology node size. Thetemperature variation of the delay being temperature dependent, the choice of aStrong-ARM or a Double-Tail hinge on the noise, power, supply voltage, and kickbackspecification. For standard power supply voltage, the Strong-ARM latch targetslow-power systems application with a high tolerance for differential kickback.To the contrary, a Double-Tail latch allows lower power supply voltage range, withlow-differential kickback. Otherwise, the Double-Tail exhibit a higher noise due tothe integration in its first stage. Tested from -40°C to 200°C, the last stage of theproposed ADC topology does not need calibration up to 180°C. The encouragingresults on this stage allows the re-use of the SAR to calibrate the previous stages.And considering the ADC, we estimate a possible resolution of 11.2-bits in 5 clockcycles per sample with an extension to 13.3-bits in 6 clock cycles with an estimatedarea of 0.12 mm2.The ADC test chip not being fabricated yet, a first step is the characterizationof the ADC. From the results of the planned measurement session, the maingoal is to push the architecture at higher sampling rates to then leverage the digitalprocessing to enhance the sampling rate without changing the analog.

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