Made available in DSpace on 2016-08-17T14:53:20Z (GMT). No. of bitstreams: 1 Tiago Brito Bezerra.pdf: 3848907 bytes, checksum: 09c5f40ad1ac5ce43a253e0335d491da (MD5) Previous issue date: 2012-04-13 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Programmable integrated circuits enable its adjustment after fabrication to fit more than one application within a certain set of applications. A programmable measurement system can be applied to the measurement of different quantities involving a set of sensors with different signal characteristics and employing a single analog-to-digital converter (ADC). The output signal range for each sensor should be adjusted to be as close to the input range of the ADC as possible, to ensure maximum measurement quality. One solution to implement the adjustment on the signal range is the use of a measurement system with programmable conditioning circuit. In this work, it is proposed to design an ADC integrated circuit whose input range is adjusted to the signal level at the output of the sensor in order to avoid amplification stages in a signal conditioning circuit. For this adjustment, the input of the converter should be programmable, making it more compatible with various sensors with different characteristics. The developed ADC also allows the configuration of the converter resolution, enabling the designer to exploit trade-offs between resolution and conversion speed for a given application. The ADC is a switched capacitor integrating converter and it was designed for the AMS 0.35 μm CMOS process. / Circuitos integrados programáveis possibilitam o seu ajuste após a fabricação, para se adequarem a mais de uma aplicação dentro de um conjunto determinado de aplicações. Um sistema de medição programável pode ser aplicado em medições que envolvam um conjunto de sensores com características diferentes de sinais e um conversor analógico-digital. A faixa de sinal em cada sensor deve ser ajustada o mais próximo da faixa de entrada do conversor analógico-digital, para garantir a medição com a faixa completa do sinal. Uma solução para realizar o ajuste da faixa do sinal é o uso de um sistema de medição com circuito de condicionamento programável. Neste trabalho de dissertação, propõe-se o projeto de um conversor analógico-digital em circuito integrado em que a faixa de entrada pode ser ajustada ao nível de sinal na saída do sensor, com a finalidade de evitar estágios de amplificação do sinal em um circuito de condicionamento. Para tal ajuste, a entrada do conversor deverá ser programável, o que o torna mais compatível com diversos sensores com características diferentes. O circuito proposto também possibilita a definição da resolução do conversor o que permite a escolha de compromisso entre resolução e velocidade de conversão, dependendo da aplicação. O conversor A/D é do tipo integrador a capacitores chaveados e foi projetado, em nível de transistor e leiaute, para o processo AMS 0,35 m CMOS.

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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch.  Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.

This thesis has its main subject pointed on possibilities of exploiting reconfigurable digital systems on FPGA basis in mixed signal applications. Description of reconfigurable and adaptive systems in general and summary of known architectures is presented in first part of this work. Next, possibilities of exploiting configurability of FPGAs in conjunction with XADC digital to analog converter are examined. These converters are provided in 7-series FPGAs and Zynq-7000 systems from Xilinx. Concept of exploiting XADC for inductance measurements is presented as alternative to existing solution - LDC1000 integrated circuit provided by Texas Instruments. Such system utilizing FPGA and XADC would come with a lot of benefits: better system integration, better signal processing options, possibility of constructing adaptive system with numerous sensory elements and last but not least, lower system cost. Advantages and disadvantages of such approach are analyzed in the very final part of this work and possible options for extension of this work are presented.

L’objectif des travaux menés dans le cadre de cette thèse est le déploiement d’un dispositif médical embarqué et portable assurant l’acquisition et la transmission du signal biomédical électrocardiogramme. Il doit intégrer des techniques de traitement avancées et un étage de communication radio. A la quête de nouvelles idées non encore explorées par la communauté scientifique, nous proposons dans notre travail d’appliquer une acquisition compressée intelligente par exploitation du caractère parcimonieux du signal électrocardiogramme à l’aide d’un convertisseur analogique-numérique à échantillonnage non-uniforme. / The objective of this thesis is the deployment of an embedded and portable medical device for acquisition and transmission of the biomedical electrocardiogram signal. The device incorporates advanced processing techniques and a radio communication module. In search of new ideas not yet explored by the scientific community, we propose in our work to apply an intelligent compressed acquisition by exploiting the sparsity character of the electrocardiogram using a non-uniform sampling analog-to-digital converter.

Thesis (M.A. (Communication studies)) -- University of Limpopo, 2019 / The rates of Internet uses are still devastatingly low especially in developing countries and South Africa is no exception. However, South Africa has had a state policy commitment to attain Internet access for those who have been unconnected in the post Apartheid era (Electronic Communication Act, No 36 of 2005). The problem is that the policy application has been one-sided, only focusing on providing public fixed Internet access through community libraries, Thusong service centres, hospitals and public schools. While this effort is credible, it does little to address the upsurge of mobile Internet access that is increasingly characterising the digital age. The age of digital mobility represents a shift from fixed public Internet access to individualised mobile Internet access through mobile phones. However, the high prices of mobile Internet data make Internet access exclusionary in South Africa, making the needy persons to remain outside of the digital revolution. This study explored issues regarding the high cost of Internet data in South Africa and suggests ways on how universal service and access policy can be formulated to focus on individualised mobile Internet connection. Using a mixed method approach, a convenience sampling technique was used to recruit 200 University of Limpopo students to participate in a survey, and a purposive sampling technique was used for selecting one official from the Independent Communication Authority of South Africa (ICASA) and another official from the Universal Service and Access Agency of South Africa (USAASA) to participate in the standardised semi structured interview. The results indicate that unless the universal service and access policy focuses on addressing the individualised mobile Internet access for needy persons, tapping the benefits that the Internet provides will remain out of reach for many South African youths.

Dans l’âge des objets connectés, circuits conventionnels implémenté sur silicium ne sont pas la seule option pour réaliser des interfaces des capteurs. Dispositifs électroniques implémentés sur substrats souples sont aussi une option intéressante comme interface des capteurs dans notre quotidien, e.g: dans des vêtements, emballages, peau et dedans notre corps humain. Dans cette thèse nous proposons une formalisation de :-La procédure de fabrication de transistors en utilisant des matériaux organiques et flexibles. -La conception de circuits analogiques et numériques en utilisant ces transistors. Les contributions de cette thèse sont :• Optimisation de la procédure de fabrication et caractérisation de 2 technologies : la première fabriqué en utilisant des masques (« shadow masks » en anglais) avec un procès relativement « simple à implémenter ». La deuxième par un procès en utilisant la photolithographie et l’auto alignement. • Modélisation et extraction de paramètres pour prévoir leurs variations dans la conception de circuits.• Customisation des outils CAO « Open Source » VLSI (Alliance ©) pour la conception des circuits et layouts des transistors organiques.• Conception, fabrication et mesure des circuits analogiques (OTAs, comparateurs et convertisseurs analogiques-numériques) et circuits numériques simples (inverseurs, portes logiques, bascules). Ce travail a eu des résultats intéressants et il ouvre un ample spectre d’applications dans l’avenir dans le domaine de l’électronique flexible et organique. / In the era of “Internet of Things”, conventional silicon-based circuits are not the only option to realize sensor interfaces. Electronic devices based on flexible materials are an interesting approach to interface with sensors connected to our everyday life, e.g.: clothes, packages, skin and into the human body. In this thesis, we propose a formalization of the:- Transistor fabrication process using organic and flexible materials.- Analog and digital circuit design using these transistors. The main contribution of this work can be summarized in the following:- Optimization of the fabrication and characterization process of two technologies: the first by shadow masks with an easy-to-fabricate procedure, the second by self-alignment and photolithography.- Modeling and parameter extraction for process variation aware analog design.- Customization of an open source VLSI CAD tools (Alliance©) for circuit design and layout of OTFT.- Design, fabrication and measurement of OTFT analog front-ends (OTAs, Comparators, Analog-to-Digital Converters,…) and basic digital circuits (Inverters, Logic Gates, …).This work achieved very interesting results and it opens a wide scope of future applications in the field of Flexible organic electronics.

Les besoins en débit d’information à transmettre ne cessent de croitre. Aussi la généralisation des émetteurs-récepteurs large-bande implique l’intégration de solutions sur une technologie silicium CMOS afin que leur cout soit compatible avec une application grand public. Si l’intégration massive des traitements numériques est facilitée par les dernières technologies CMOS, la fonction de conversion analogique-numérique est quant à elle plus difficile. En effet, afin d’optimiser l’étage frontal analogique, le convertisseur analogique-numérique (CAN) doit répondre à des contraintes très fortes en termes de largeur de bande (de l’ordre du GHz) et de résolution (de 10 à 14bits). Les convertisseurs analogique-numérique basés sur l’entrelacement temporel (CAN-ET) connaissent un essor remarquable car ce sont aujourd’hui les seuls à pouvoir répondre aux deux contraintes énoncées ci-dessus. Cependant, cette structure de CAN reste sensible aux défauts d’appariement entre ses différentes voies de conversion et voit ses performances limitées par la présence de raies parasites liées à des erreurs statiques (offset et gain) et dynamiques (skew et bande passante). Pour réduire l’impact des erreurs dynamiques, nous avons implémenté une calibration mixte en technologie FD-SOI 28nm. Dans une première partie, un état de l’art portant sur les différentes techniques de minimisation et de compensations analogiques des erreurs de skew et bande passante est réalisé. A partir de cette étude, nous proposons différentes techniques analogiques pour compenser les d´esappariements de bande passante et de skew. Pour compenser le skew, nous profitons des avantages de la technologie FD-SOI en modulant fortement la tension de la face arrière d’un ou plusieurs transistor(s) d’ échantillonnage. Concernant l’erreur de bande passante, nous proposons d’ajuster la résistance équivalente du T/H en adaptant la résistance à l’état passant des transistors d’échantillonnage de cinq manières différentes. Pour définir parmi toutes les compensations proposées celle qui est la plus adaptée à nos besoins, nous comparons différents critères de performance. Après avoir identifié la meilleure compensation de skew et de bande passante, nous avons, dans une dernière partie, implémenté une calibration mixte des erreurs statiques et dynamiques o`u l’estimation numérique est basée sur la méthode des Moindres Carrés. / Data transmission requirements are ever more stringent, with respect to more throughput, less power consumption and reduced cost. The cable TV market is where broadband transceivers must continuously innovate to meet these requirements. In these transceivers, the analog front-end part must be adapted to meet the increasingly tighter specifications of the newest standards. A key bottleneck is the Analogto- Digital Converter (ADC), which must reach a sampling rate of several Gigasamples per second at effective conversion resolutions in the range of 10 to 14 bits. Among the possible choices, converters based on Time-Interleaving (TI-ADC) are experiencing remarkable growth, and today they appear to be the best candidates to rmeet the two constraints set out above. However, TI-ADCs are hampered by mismatches between its different conversion channels, which result in degraded performance due to the appearance of mismatch spurs in the frequency domain, arising both from static errors (gain and offset mismatch) and dynamic (skew and bandwidth) errors. To reduce these errors, we have investigated a mixeddomain calibration strategy for TI-ADCS in 28nm FDSOI technology. We strongly focused the analog compensation of dynamic errors. This report begins with a review of the state-of-theart w.r.t. the mismatch reduction and analog compensation techniques for both dynamic errors. Based on these results, we then introduce a variety of analog techniques aimed at compensating the bandwidth and skew mismatches. In order to compensate for the skew, we make the most of the FD-SOI technology by tightly regulating the voltage of the back gate of one or several sampling transistors. For the bandwidth error, we recommend that the T/H equivalent resistor be adjusted, adapting the on-resistor of the sampling transistors using up to five different techniques. Once the most appropriate skew and bandwidth compensations were identified, we ultimately implemented a mixed calibration of static and dynamic errors along with a digital calculation based upon the "Least- Squares" method.

L’imagerie constitue un axe majeur de l’exploration de l’univers et de la Terre depuis l’espace, que l’on se trouve dans le domaine du visible ou non. Ainsi dans le domaine spatial, les données sont le plus souvent récupérées par un capteur CCD (Charge-Coupled Device, ou Dispositif à Transfert de Charge (DTC)) qui fournit des tensions analogiques vers un convertisseur analogique-numérique (CAN), dont la sortie sera transmise à une chaîne de traitement, puis envoyée sur terre. Ainsi, les CAN sont des éléments clés dans l’imagerie par satellite. De leur précision et de leur vitesse va dépendre la qualité de la représentativité de la chaîne de signaux binaires. Il est donc crucial de réaliser une conversion de données de grande qualité (vitesse, précision) tout en s’assurant de la résistance du CAN à l’environnement radiatif. L’objectif de cette thèse est d’améliorer la robustesse à l’environnement spatial, tout en optimisant les performances, de plusieurs fonctions élémentaires d’un convertisseur analogique-numérique de type pipeline 14bits,5MS/s, réalisées en technologie XFAB 0,18µm. Les trois fonctions ciblées sont les interrupteurs (notamment la résolution des problèmes liés au phénomène d’injection de charges en environnement spatial), les comparateurs (durcissement) et l’amplificateur à capacités commutées (amélioration du gain par une technique prédictive sans pénaliser la puissance consommée). / Imaging is a major issue in the observation of the Universe and the Earth from space, whether in the visible domain or not. Thus, in the spatial field, data is often gathered by a CCD (charge-Coupled Device) sensor, that supplies analog voltages to an Analog-to-Digital Converter (ADC), which outputs will be delivered to a processing chain, and then sent to earth. Consequently, ADCs are key elements in satellite imaging. Their precision and speed will indeed define the quality and the representativeness of the binary signal. It is then crucial to perform a high quality (speed & precision) conversion of the data, while making sure that the ADC can cope with the harsh irradiative environment. The purpose of this thesis is to improve the robustness to the space environment (hardening), while optimizing the performances, of several elementary devices that compose a 14 bits, 5MS/s pipeline ADC, made with the XFAB 180nm technology. The three targeted functions are the switches (especially the problems linked to coping with the charge injection problems in a space environment), the comparators (hardening) and the switched-capacitor amplifier (gain boosting through a predictive architecture with no penalty on the power consumption).

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