Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels. The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme. A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations. A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs. / <p>QC 20150422</p>

La tendance du secteur automobile à développer des capteurs etactionneurs intelligents, faire cohabiter l’électronique analogique et l’électroniquenumérique devient un art. Placé au sein des actionneurs, pour la sécurité et le confortdes passagers, les convertisseurs analogique-numérique (CAN) sont les composantsclés de ces systèmes intelligents. Un CAN rapide, précis, et peu cher serévèle être un précieux allié pour les équipementiers automobiles. Pour diminuerles coûts, et faciliter l’utilisation de ce bloc, la surface de silicium occupée doit êtreconsidérablement réduite à moins de 0.5mm2. Quant à la précision du convertisseur,12-bits tous les 5 coups d’une horloge de 100 MHz sont nécessaires pour unetempérature de -40°C à 175°C.Ce travail de recherche se focalise sur l’amélioration de l’efficacité énergétiquesous les contraintes que l’environnement automobile représente. Notre principalecontribution réside dans le développement par une approche top-downd’une nouvelle architecture à 3 étages de topologies différentes. Le premier étageest un ΣΔ-Incrémental intrinsèquement linéaire. Le second étage est un algorithmiquepour augmenter rapidement la résolution. Enfin, un SAR accroît la résolutionavec faible consommation de puissance et surface de silicium.Suite à l’analyse de 40 années d’état de l’art, la nouvelle architecture proposéefut validée par vérification des non-linéarités statiques (DNL, INL) à différentsniveaux de modélisation. Commençant par un modèle MATLAB sans leslimitations analogiques, le niveau de modélisation se raffine petit à petit jusqu’auniveau transistor du convertisseur. Un modèle Verilog-A permit la déterminationdes spécifications minimales des briques de base analogiques: les comparateurs etles amplificateurs à transconductance. La sensibilité de ces derniers à la températurefut analysée pour limiter les erreurs commises sur les tensions analogiques.Une fois dessinés et les parasites extraits, les modèles variant avec la températureremplacent leurmodèle Verilog-A respectif afin d’obtenir les performances finales.Parallèlement, deux architectures de comparateurs ont été évaluées en températureau sein d’une première puce de test. Deux méthodes ont été utilisées pour estimerl’offset des comparateurs, et un nouveau circuit asynchrone estime le délai.Une seconde puce de test permet de vérifier la sensibilité du SAR à la températuremalgré un fonctionnement pseudo-asynchrone.Pour les comparateurs, le nouveau circuit de mesure différentielle du retardmontre une précision de 60 ps dans le pire des cas, pour la plus petite surface surpuce connue en considérant la technologie utilisée. Comme la variation du retardest dépendante de la température, le choix d’un Strong-ARM (SA) ou d’un Double-Tail (DT) dépendra du bruit, de la puissance, de la tension d’alimentation, et de laspécification de kickback. Pour une tension d’alimentation standard, les SA comparateursciblent les systèmes à faible consommation avec une tolérance élevéepour le kickback différentiel. Au contraire, les DT comparateurs acceptent uneplage de tension d’alimentation plus faible, et présentent un faible kickback différentiel,mais un bruit plus important. Testé de -40°C à 200°C, le dernier étagedu CAN proposé, n’a pas besoin d’être calibré jusqu’à 180°C. Les résultats encourageantssur cet étage permettent la réutilisation de celui-ci pour calibrer les étagesprécédents. Et pour le CAN, nous estimons une résolution possible de 11,2 bitsen 5 cycles d’horloge par échantillon avec une extension à 13,3 bits en 6 cyclesd’horloge. La surface estimée est de 0,12mm2.La puce de test pour le CAN est en cours de finalisation, une première étapesera sa caractérisation. Les résultats de cette session de mesure détermineront s’ilest possible de pousser l’architecture à des fréquences plus élevées pour ensuitetirer parti du traitement numérique pour conserver les performances. / In the automotive industry, the trend being to develop smartsensors and actuators, the on-board electronic has been ever more an artful workto combine analog electronics and the digital one. While many monitoring andcontrol systems play a crucial role as well for the safety as for the comfort of passengers,small components, like ADCs, are mandatory as a building block or as anessential functionality integrated into smart actuators. To that extent, a low-cost,fast and accurate analog to digital converter operating in those harsh conditionsis a good ally for equipment manufacturers. To decrease the cost, the area is ofprimary concern. Considering re-use of the ADC as an IP-bloc, the area has beenlimited to less than half a square millimeter for an low-oversampling ratio of 5 tooutput a 12-bit code at a sample rate of 20 MSamples/s, over a wide temperaturerange from-40°C to 175°C.This work focuses on the design of high-precision, high-speed and energyefficient ADC under the harsh environment the automotive one represents. Ourmain contribution relies on the development of an new hybrid topology proposalusing 3 stages to cope with such constraints based on a top-down approach: A firstcounting stage inherently linear, an algorithmic stage allowing to increase rapidlythe precision, and a SAR stage, ideal in terms of area and consumption, for a lownumber of bits.Based on a 40 years literature review, a new topology proposal has been validatedby checking its static metric of non-linearity (DNL, INL) at different level ofmodelisation. Starting by a MATLAB implementation without analog limitations,we refined step by step the model tillwe reach a transistor level of the ADC. Thence,Verilog-A model allows us to fix the minimum requirements of the key analog buildingblocks, to wit comparators and OTA. The latter has been analysed in order tolimit the settling error sensitivity to the temperature. Laid-out, parasitic extractedsimulation results of these considering PVT variations, they replace then previoushigh-level model to give final performances. Meanwhile, two well-known comparatorarchitectures have been assessed as IP blocs inside a first test chip. To performthe offset extraction, both a conventional and a feedback loop have been inspected.To assess, the delay a new asynchronous circuit has been proposed. A secondchip tests the sensitivity of the SAR to validate both the pseudo-asynchronousdigital scheme, and a Double-Tail comparator in real operating conditions.For comparators, the new differential measurement circuit of the delaydemonstrate an accuracy of 60 ps in the worst case, over a large temperature rangefor the smallest chip area known with respect to the technology node size. Thetemperature variation of the delay being temperature dependent, the choice of aStrong-ARM or a Double-Tail hinge on the noise, power, supply voltage, and kickbackspecification. For standard power supply voltage, the Strong-ARM latch targetslow-power systems application with a high tolerance for differential kickback.To the contrary, a Double-Tail latch allows lower power supply voltage range, withlow-differential kickback. Otherwise, the Double-Tail exhibit a higher noise due tothe integration in its first stage. Tested from -40°C to 200°C, the last stage of theproposed ADC topology does not need calibration up to 180°C. The encouragingresults on this stage allows the re-use of the SAR to calibrate the previous stages.And considering the ADC, we estimate a possible resolution of 11.2-bits in 5 clockcycles per sample with an extension to 13.3-bits in 6 clock cycles with an estimatedarea of 0.12 mm2.The ADC test chip not being fabricated yet, a first step is the characterizationof the ADC. From the results of the planned measurement session, the maingoal is to push the architecture at higher sampling rates to then leverage the digitalprocessing to enhance the sampling rate without changing the analog.

This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Telemetry & Instrumentation, in conjunction with NASA’s Kennedy Space Center, has developed a commercial, intelligent, data acquisition module that performs all functions associated with acquiring and digitizing a transducer measurement. These functions include transducer excitation, signal gain and anti-aliasing filtering, A/D conversion, linearization and digital filtering, and sample rate decimation. The functions are programmable and are set up from information stored in a local Transducer Electronic Data Sheet (TEDS). In addition, the module performs continuous self-calibration and self-test to maintain 0.01% accuracy over its entire operating temperature range for periods of one year without manual recalibration. The module operates in conjunction with a VME-based data acquisition system.

Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3.84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamique.

Cette thèse est le fruit d'un partenariat entre la BL TVFE de NXP Semiconductors et l'ESIEE dans le cadre d'une thèse CIFRE. Le but est d'apporter une solution qui permette la réception de plusieurs canaux pour le câble. Ce sujet est lié à la problématique de numérisation large bande. Dans la première partie, nous faisons un état-de-l'art sur les convertisseurs analogiques-numériques (CAN), sur les architectures parallèles (entrelacement temporel et bancs de filtres hybrides (BFH)), et sur les méthodes d'échantillonnage (passe-bande et complexe). Puis, nous étudions une architecture composée d'un banc de filtres analogiques et un banc de CANs. Nous cherchons à réduire surtout le taux d'échantillonnage. Nous comparons notre solution à un CAN large bande performant, avec notre fonction de coût. L'un des avantages de cette architecture est que tous les composants sont faisables, même les CANs, et qu'il est possible d'éteindre des sous-bandes pour diminuer la consommation. Cette solution est intéressante pour le moment mais n'est pas compétitive en termes de consommation et de surface. Nous proposons une alternative dans la partie 3, avec les BFH. Nous étudions cette architecture, en gardant à l'esprit la faisabilité de la solution. Nous avons choisi un BFH à deux voies, avec un filtre analogique passe-bas et un passe-haut. Puis, nous proposons un algorithme d'optimisation des filtres de synthèse pour atteindre nos objectifs de distorsion et de réjection de repliement. Une identification des filtres analogiques est aussi présentée. Finalement, une réalisation physique prouve le concept et valide les limitations théoriques de cette architecture / This thesis is a partnership between the BL TVFE of NXP Semiconductors and ESIEE. Its goal is to provide a solution to multi-channel reception for cable network. This is linked to the problematic of broadband digitization. In the first part, the state-of-the art of ADCs, parallel architectures (TI and HFB) and sampling methods (bandpass sampling and complex sampling) is recalled. Then we study an architecture called RFFB with a bank of analog filters and a bank of ADCs. We try to reduce the constraints on ADCs, especially the sampling rate with the different sampling. We propose an interesting solution to broadband digitization and compare this solution to a challenging wideband ADC, using the cost function we introduce. This architecture has the major advantage that all the components are feasible, even the ADCs, and it is possible to switch-off subbands to save power. It could be a good solution at the present time but it is not competitive in terms of power consumption and surface. An alternative is proposed in Part 3, where we study Hybrid Filter Banks. It is interesting to study this architecture with realization feasibility in mind. This is why we select a 2-channel HFB with a lowpass filter and a highpass filter as analog filters. Then we propose an efficient optimization algorithm to find the best synthesis filters and reach our targets of distortion and aliasing rejection. An identification of analog filters is also suggested to cope with the issue of sensitivity to analog errors. Finally, a physical realization proves the concept of aliasing rejection and confirms the theoretical issues of this architecture

High precision tightening of nuts and bolts together with traceability are important in many industrial assembly lines. To achieve this the nutrunner needs to accurately measure the torque which is applied to the nut, process the signal and provide the information to the controller that controls the tightening process. This is done by having a strain gauge in form of a Wheatstone bridge connected to the tightening shaft. When an excitation voltage is applied to the bridge the applied torque to the shaft can be measured in form of a voltage difference. This voltage is amplified, filtered and converted to a digital signal, this is referred to as the signal chain. Atlas Copco has provided an example of how the signal chain looks in today’s application. The signal chain consists of a gain stage and a filter stage, and the analog-to-digital conversion process is performed internally in an MCU together with several advanced digital filters. The purpose of this thesis is to analyse this signal chain, it’s performance in regards to noise and investigate if the chain can be redesigned with the same or better noise performance with other components. It should also be investigated if the conversion process can be moved from the MCU to an integrated circuit component to reduce the effects of noise from the tool motor. Hence, in addition to noise, other specifications such as power supply and physical footprint is also considered in the thesis. The goal is to define a process on how to analyse the noise, precision, speed and footprint in a front end signal chain. In addition to that, one or more alternative signal chains should be presented if the requirements of the front end can be fulfilled. A lot of effort went into researching how noise impacts a signal chain to get a thorough understanding on how to improve/rebuild an already functioning signal chain. The result was a working process on how to analyse the noise in a front end signal chain like the one described above, together with a generic noise simulation model in LTSpice which can be used if a component does not have a spice model. With the model a few alternative signal chains were considered which fulfills the noise requirements and the best performing alternative was built on a PCB in KiCAD. However, the physical PCB has not been tested due to the limited timeframe of the project and therefore only calculations and simulations act as the verifying element of the function. / Högprecisionsåtdragning av skruvar och bultar är en viktig del av många industriella tillverkningsprocesser. I detta ingår ofta spårbarhet som en viktig del för att kunna kvalitetssäkra processerna. För att åstadkomma detta måste skruvdragaren kunna mäta det moment som appliceras vid en åtdragning, bearbeta denna signal och tillhandahålla den till kontrollenheten som styr åtdragningsprocessen. Momentmätningen görs med en töjningsgivare, ofta av typen Wheatstonebrygga, som kopplas till verktygets axel. När en excitationsspänning kopplas till bryggan kan momentkraften i axeln mätas i form av en spänningsskillnad. Denna analoga signal blir sedan förstärkt, filtrerad och omvandlad till en digital signal. Denna process benämns som signalkedjan. Företaget har tillhandahållit ett exempel på hur en sådan signalkedja ser ut i en av deras nuvarande verktyg. I dagens utförande sker signalomvandlingen internt i en mikrokontroller, där den också filtreras med digitala filter. Syftet med denna avhandling är att analysera signalkedjan, dennas prestation i förhållande till brus, och undersöka ifall signalkedjan kan återskapas med samma eller bättre brusegenskaper med andra komponenter. Det undersöks även om signalomvandlingen kan flyttas från mikrokontrollern till en integrerad krets-komponent för att minska signalens påverkan från brus från verktygets motor. Som led i detta kommer även kretsens fysiska fotavtryck undersökas då det styr var på verktyget kretsen kan monteras. Målet är att definiera en process för att analysera brus, precision, hastighet och fotavtryck i ett signalgränssnitt av denna typ. Utöver detta skall en eller flera förslag till alternativa signalkedjor presenteras om de kan uppfylla kraven på gränssnittet. Mycket ansträngning gick till att undersöka hur brus påverkar en signalkedja för att få en grundlig förståelse av hur man kan förbättra och/eller bygga om en befintlig signalkedja. Resultatet blev en fungerande teoretisk analysprocess av brus i en signalkedja i ett gränssnitt av den typen som beskrivs ovan. Ytterligare resultat var en generell brussimuleringsmodell i LTSpice som kan användas då en komponent saknar Spice-modell. Med hjälp av modellen utvärderades några alternativa signalkedjor utifrån deras brusegenskaper och utifrån det bästa alternativet togs en PCB-layout fram i KiCad. Några tester på en fysisk krets har dock inte gjorts då tidsramen för projektet inte tillät tillverkning av kretskortet. Därför utgår utvärderingen av kretsens funktion enbart från teoretiska beräkningar och simuleringar.

Neste trabalho é apresentado o desenvolvimento de instrumentação eletrônica para controle e automação de um sistema de crescimento de semicondutores por Epitaxia por Feixes Moleculares. Envolve uma variedade de circuitos analógicos e digitais como: um módulo de aquisição de dados e controle baseado em uma UCP Z-80, contendo algumas interfaces digitais e analógicas multiplexadas, e comunicando-se com um microcomputador através de uma interface serial. Envolve ainda o desenvolvimento de controladores de temperatura analógicos tipo P.I.D., atuação por motores de passo e circuitos de condicionamento de sinal. / In this work is presented the development of electronic instrumentation for automation and control of a Molecular Beam Epitaxy semiconductor growth system. A variety of analog and digital instrumentation circuits have been designed and implemented, including a data acquisition and control system based on a Z-80 CPU, which controls some multiplexed digital and analog interfaces and talks to a microcomputer using serial communication. Other circuits have been also developed, including analog temperature controllers, stepper motor actuators and circuits for signal conditioning.

Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (plusieurs Watts) donc peu efficaces énergétiquement. Cette thèse explore différentes approches d’optimisation de l’efficacité énergétique des CAN "flash". Afin de min- imiser la consommation du CAN, il n’y a pas d’Echantillonneur-Bloqueur (EB) en tête du circuit. Les étages d’entrée du codeur sont ainsi exposés à la pleine bande passante du signal, à savoir DC-10GHz. Ceci impose des contraintes très strictes sur la précision temporelle de la détection et de la quantification du signal. L’essentiel de cette thèse est donc concentré sur l’analyse des effets hautes frèquences impactant la conception des éléments frontaux du CAN. La validité et l’efficacité des méthodes présentées sont démontrées par des mesures autour d’un CAN 6 bit 20 GS/s. En em- pruntant les techniques de conception des circuits ultra-rapides et en exploitant le po- tentiel haute-fréquence de la technologie à l’état de l’art SiGe BiCMOS, un circuit complètement analogique a ainsi pu être réalisé. Ce CAN est mono-voie et n’a besoin d’aucune calibration ou correction, ni d’assistance digitale. Avec à peine 1W, ce cir- cuit atteint un record d’efficacité énergétique dans l’état de l’art des CAN rapides non entrelacés. / High speed Analog-to-Digital Converters (ADC) are essential building blocks for the reception and processing in high data rate reception circuits. The flash ADC archi- tecture performs the digitization by comparing the analog input signal to all refer- ence levels of the quantization range simultaneously and is thus the fastest architecture available. In the past the flash architecture has been employed successfully to digitize signals at Nyquist rates beyond 20 GS/s. However the inherent high speed operation has led to power consumptions of several watts and hence to poor energy efficien- cies. This thesis explores approaches to optimize the energy efficiency of flash ADCs. In particular, no dedicated track-and-hold stage is used at the high speed data input. This imposes very stringent requirements on the timing accuracy and level accuracy in the high speed signal distribution to the comparators. The comparators need to ex- hibit a very high speed capability to correctly perform the quantization of the signal against the reference levels. The main focus of this thesis is hence the investigation of design relevant high frequency effects in the analog ADC frontend, such as the bandwidth requirement of overdriven comparators, the data signal distribution over a passive transmission line tree and the dynamic linearity of emitter followers. The correctness and efficacy of the presented methods is demonstrated by measurement results of a 6 bit 20 GS/s Nyquist rate flash ADC fabricated within the context of this work. The demonstrator ADC operates without time interleaving, no calibration or correction whatsoever is needed. By employing design techniques borrowed from high speed analog circuits engineering and by exhausting the high speed potential of a state-of-the-art SiGe BiCMOS production technology, a flash ADC with a record energy efficiency could be realized.

Neste trabalho é apresentado o desenvolvimento de instrumentação eletrônica para controle e automação de um sistema de crescimento de semicondutores por Epitaxia por Feixes Moleculares. Envolve uma variedade de circuitos analógicos e digitais como: um módulo de aquisição de dados e controle baseado em uma UCP Z-80, contendo algumas interfaces digitais e analógicas multiplexadas, e comunicando-se com um microcomputador através de uma interface serial. Envolve ainda o desenvolvimento de controladores de temperatura analógicos tipo P.I.D., atuação por motores de passo e circuitos de condicionamento de sinal. / In this work is presented the development of electronic instrumentation for automation and control of a Molecular Beam Epitaxy semiconductor growth system. A variety of analog and digital instrumentation circuits have been designed and implemented, including a data acquisition and control system based on a Z-80 CPU, which controls some multiplexed digital and analog interfaces and talks to a microcomputer using serial communication. Other circuits have been also developed, including analog temperature controllers, stepper motor actuators and circuits for signal conditioning.