Cache side-channel attacks have evolved alongside increasingly complex microprocessor architectural designs. The attacks and their prevention mechanisms, such as cache partitioning, OS kernel isolation, and various hardware/operating system enhancements, have similarly progressed. Nonetheless, side-channel attacks necessitate effective and efficient prevention mechanisms or alterations to hardware architecture. Recently, machine learning (ML) is an emerging method for detecting and defending such attacks. However, The effectiveness of machine learning relies on the dataset it is trained on. The datasets for training these ML models today are not vast enough to enhance the robustness and consistency of the model performance. This thesis aims to enhance the ML method for exploring various cache side-channel attacks and defenses by offering a more reasonable and potentially realistic dataset to distinguish between the attacker and the victim process. The dataset is gathered through a computer system simulation model, which is subsequently utilized to train both the attacker and detector agents of the model. Different ways to collect datasets using the system simulation are explored. A New Dataset for training and detecting cache side-channel attacks is also explored and methodized. Lastly, the effectiveness of the dataset is studied by training a Flush+Reload attacker and detector model performance. / Master of Science / Imagine a spy trying to steal secret information from a computer by listening to its clicks and whirs. That's kind of what a side-channel attack is. The computer uses a special memory called a cache to speed things up, but attackers can spy on this cache to learn bits and pieces of what the computer is working on. Numerous ways to mitigate such attacks have been proposed, but they were either costly to implement in terms of resources or the performance offset of the computer is large. New types of attacks are also being researched and discovered. More recently, Machine learning (ML) models are used for detecting or defending cache side-channel attacks. Currently the training ground truth or the input dataset for the ML models is not vast enough to enhance the robustness and consistency of the model performance. This thesis project aims to enhance the ML approach for exploring and detecting existing and unknown Cache side-channel attacks by offering a more reasonable and potentially realistic training ground (dataset). The dataset is gathered through a computer system simulation model, which is subsequently utilized to train the ML models. Different ways to collect datasets using the computer system simulation are explored. A New Dataset for training and detecting Cache side-channel attacks is also explored and methodised. Lastly, the effectiveness of the dataset is studied by training a Flush+Reload attacker performance.

Service failures are common in the hospitality industry and are often associated with low guest satisfaction. However, guest satisfaction is possible to be restored when excellent service recovery tactics are deployed in a timely fashion. The temporary unavailability of a service offering is a type of failure recognized by practitioners, customers, and the research community, yet it is typically only used for illustrative purposes in research. Given the ubiquity of this type of failure in the industry, the lack of investigations of its various aspects (e.g., communication of the occurrence to the customer, reasons, ramifications, etc.) seems surprising. Using scenario-based experimental design in a restaurant setting, this research tested the effects of timing (early/ late) of the communication of the temporary unavailability of a menu item on customers' satisfaction with the recovery, while taking into account the perceived severity of the failure as well as the relationship between customer and provider. Findings indicate that restaurant guests informed early that a menu item is unavailable are more satisfied than those who are informed later in their dining experience (after they have been given time to study the menu and make choices). This increased satisfaction is mediated through the customers' perception of interactional, procedural, and distributive justice. / Doctor of Philosophy / Things go wrong all the time in the hospitality industry; knowing how and when to address guests can make or break a business. For restaurants, the unavailability of a menu item is often an uncontrollable occurrence. In a scenario-based experiment, the present study tested guests' reactions to restaurant staff communicating the unavailability of an item early (during introductions) versus late (after the guests were given time to peruse the menu and make choices). The study took into account the type and duration of the relationship between guest and provider, as well as the fact that the guest may either be particularly interested in the unavailable item or indifferent. The results overwhelmingly pointed in one direction: the sooner the issue is communicated to the guests, the better. Respondents who were told early in their dining experience about a menu item being unavailable were significantly more satisfied than their counterparts (who weren't informed until late), and, overall, perceived the provider as more just. Anecdotal evidence shows different approaches to this type of issue but prior empirical evidence appears non-existent as to which approach yields optimal results, so the findings of the present study should be relevant to practitioners trying to retain guests after things have gone wrong.

<p dir="ltr">Previous research has documented rye (Secale cereale L.) cover crop (RCC) benefits on weed suppression, erosion control, and water quality. However, RCC adoption is often low prior to corn (Zea mays L.) due to observed yield losses caused by a RCC. Therefore, further research is required to understand and develop corn agronomic, planting equipment, and N fertilizer timing recommendations following a RCC to minimize crop stress and yield losses. The objective of this research was to evaluate corn performance and yield in response to different N fertilizer application timings and after-market closing wheel types following a RCC using multiple field-scale environments. Treatments within the N timing study included three N fertilizer timings (2x2 starter + V5 sidedress, 2x2 + V10, and 2x2 + V5 + V10) and two RCC treatments (RCC and no RCC). Treatments within the closing wheel study included three closing wheel types: Standard Rubber (SR), Cruiser Extreme (CE), and Cupped Razor (MCR), and two RCC treatments (RCC and no RCC. Both studies were conducted at field-scale using commercial equipment at four locations in Indiana in 2022 and 2023. In the N timing study a significant (P<0.1) RCC x N timing interaction was observed in 5 of 6 site-years, indicating optimum N fertilizer timing differs with the presence of a RCC. Without the inclusion of a RCC, the use of a 5x5 + V10 or 5x5 + V5 + V10 N application decreased yield in 4 of 6 and 0 of 6 site-years, respectively when compared to a 5x5 + V5 N application. Whereas, with a RCC the use of a 5x5 + V10 or 5x5 + V5 + V10 N decreased yield in 6 of 6 and 2 of 6 site-years, respectively when compared to a 5x5 + V5 N application. In the closing wheel study, aftermarket closing wheels showed no difference in daily emergence timing and/or final plant stand in no-till conditions without a RCC. However, in RCC treatments, the CE improved total percent corn emergence [7 – 12 days after planting (DAP)] by 6 and 15% at 2 of 3 site-years. Whereas, the MCR improved percent corn emergence (7-12 DAP) by 8% in 1 of 3 site-years. Furthermore, corn grain yield was increased by 5-8 bu ac-1 at 2 of 3 site-years with CE when following a RCC and by 7 bu ac-1 at 1 of 3 site-years with MCR when following a RCC. Overall, results suggest farmers can combine the use of after-market closing wheels designed for high residue/RCC systems and optimum N fertilizer application timing (5x5 + V5 sidedress) to improve corn emergence, reduce N stress, and improve yield following a RCC.</p>

Yes / Over the past few decades the number of women having their first babies over the age of 35 in the United Kingdom (UK) has increased. Women’s timing of motherhood is invariably bound up with a discourse of ‘choice’ and in this paper we consider the role choice plays in the timing of motherhood among women who have been defined as ‘older’ mothers. This article is based on data from 11 semi-structured interviews that explored the transition to motherhood among ‘older’ middle-class mothers. The interviews were analysed using critical discursive psychology. The women drew upon two dominant repertoires when making sense of their timing of motherhood. Within the first repertoire, ‘older motherhood as circumstance’, older motherhood was presented as the outcome of life circumstances beyond their control, with a lack of the ‘right’ circumstances facilitating ‘delayed’ motherhood. Within the second repertoire, ‘older motherhood as readiness’, women constructed themselves as (now) prepared for motherhood. ‘Readiness’ was bound up with notions of self-fulfillment, yet also assessments of their ability to be ‘good’ mothers. We conclude that, far from a straightforward choice, the timing of motherhood is shaped by cultural definitions of the ‘right’ circumstances for parenthood, but also cultural definitions of ‘good’ motherhood, which may define when women are ‘ready’.

Driver violations of traffic signals are a major cause of intersection vehicle crashes. The duration of yellow intervals is highly associated with driver yellow/red time stopping behavior. Rainy weather and wet pavement surface conditions may result in changes in both driver behavior and vehicle performance. The research presented in this thesis quantifies the impact of wet pavement surface and rainy weather conditions on driver perception-reaction times (PRTs) and deceleration levels, which are used in statistical models for the design of yellow intervals. A new dataset with a total of 648 stop-run records were collected as part of the research effort during rainy weather and wet pavement surface conditions at the Virginia Department of Transportation's Smart Road facility. This experiment was conducted at a 72.4 km/h (45 mi/h) approach speed where participant drivers encountered a yellow indication initiation. The participant drivers were randomly selected in different age groups (under 40 years old, 40 to 59 years old, and 60 years of age or older) and genders (female and male). Combined with an existing dataset that was collected by the same research group under clear weather conditions during the summer of 2008, statistical models for driver PRT and deceleration levels are developed, considering roadway surface and environmental parameters, driver attributes (age and gender), roadway grade, and time to the intersection at the onset of yellow. Using the state-of-the-practice procedures with the modeled PRT and deceleration levels, inclement weather yellow timings are then developed as a function of different factors (e.g., driver age/gender, roadway grade, speed limits, and precipitation levels). The results indicate that an increase in the duration of change interval is required for wet roadway surface and rainy weather conditions. Lookup tables are developed with different reliability levels to provide practical guidelines for the design of yellow signal timings in wet and rainy weather conditions. These recommended change durations can be integrated within the Vehicle Infrastructure Integration (VII) initiative to provide customizable driver warnings prior to a transition to a red indication. / Master of Science

The Daya Bay reactor neutrino experiment is a high sensitivity experiment designed to determine the last unknown neutrino mixing angle $theta_{13}$ by measuring disappearance of reactor antineutrinos emitted from six 2.9 $GW_{th}$ reactors at the Daya Bay Nuclear Power Station. There are eight identical Gd-loaded liquid scintillator detectors deployed in two near (flux-weighted baseline 512 $m$ and 561 $m$) and one far (1579 $m$) underground experimental halls to detect the inverse beta decay interaction. This dissertation describes the Daya Bay Experiment and individual contributions to this experiment. Chapter 1 reviews the history of the neutrino and the neutrino oscillation phenomena. The reactor based neutrino experiments in different times are described in this chapter in detail. It presents the motivation of the Daya Bay Experiment. In Chapter 2, the neutrino detection method and the $theta_{13}$ relative measurement method are introduced. This chapter focuses on the design of the Daya Bay Experiment, including antineutrino detector, calibration system, muon veto system and muon tagging system. Chapter 3 shows the design, development, construction, and assembly of Muon Pool PMT calibration system, and presents an algorithm of calculating the muon pool PMT timing offset values. Chapter 4 focuses on the manufacture, installation and commissioning of RPC HV system. Chapter 5 presents the analyses of the radioactive isotopes induced by comic muons. The Daya Bay detector energy response model is also described in detail. The relative rate analysis results exclude a zero value from $sin^22theta_{13}$ with a significance of 7.7 standard deviation using 139 days of data, 28909 (205308) antineutrino candidates which were recorded at the far hall (near halls) and shows $sin^22theta_{13} = 0.089pm0.011$ in a three-neutrino framework. A combined analysis of the $overline nu_e$ rates and energy spectra based on the detector energy response model improved measurement of the mixing angle $sin^22theta_{13} = 0.090^{+0.008}_{-0.009}$ by using 217 days of data, 41589 (203809 and 92912) antineutrino candidates were detected in the far hall (near halls). Also the first direct measurement of the $overline nu_e$ mass-squared difference $|Delta m^2_{ee}|= (2.59^{+0.19}_{-0.20})times10^{-3}$ $eV^2$. It is consistent with $|Delta m^2_{mumu}|$ measured by muon neutrino disappearance, supporting the three-flavor oscillation model. / Ph. D.

According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This causes an exponential increase of the available area, and hence,the complexity of modern digital designs. This consistent enormous gross challenges different research areas in Electronic Design Automation (EDA). Thus, various EDA applications such as equivalence checking, model checking, Automatic Test Pattern Generation (ATPG), functional Bi-decomposition, and technology mapping need to keep pace with these challenges. In this thesis, we are concerned with improving the quality and performance of different EDA algorithms particularly in area of hardware verification and synthesis. First, we introduce algorithms to manipulate Reduced Ordered Binary Decision Diagrams (ROBDD) on multi-core machines. In order to perform multiple BDD operations concurrently, our algorithm uses a breadth-first search (BFS). As ROBDD algorithms are memory-intensive, maintaining locality of data is an important issue. Therefore, we propose the usage of Hopscotch hashing technique for both Unique Table and BFS Queues to improve the construction time of ROBDD on the parallel platform. Hopscotch hashing technique not only improves the locality of the manipulating data, but also provides a way to cache recently performed BDD operation. Consequently, The time and space usage can be traded off. Secondly, we used static implications to enhance the performance of SAT-based Bounded Model Checking (BMC) problem. we propose a parallel deduction engine to efficiently utilize low-cost off-shelf multi-core processors to compute the implications. With this engine, we can significantly reduce the computational processing time in analyzing the deduced implications. Secondly, we formulate the clause filter problem as an elegant set-covering problem. Thirdly, we propose a novel greedy algorithm based on the Johnson's algorithm to find the optimal set of clauses that would accelerate BMC solution. Thirdly, we proposed a novel synthesis paradigm to achieve timing-closure called Timing-Aware CUt Enumeration (TACUE). In TACUE, optimization is conducted through three aspects: First, we propose a new divide-and-conquer strategy that generates multiple sub-cuts on the critical parts of the circuit. Secondly, cut enumeration have been applied in two cutting strategies. In the topology-aware cutting strategy, we preserve the general topology of the circuit by applying TACUE in only self-contained cuts. Meanwhile, the topology-masking cutting strategy investigates circuit cuts beyond their current topology. Thirdly, we proposed an efficient parallel synthesis framework to reduce computation time for synthesizing TACUE sub-cuts. We conducted experiments on large and difficult industrial benchmarks. Finally, we proposed the first scalable SAT-based approaches for Observability Dont Care (ODC) clock gating. Moreover we intelligently choose those inductive invariants candidates such that their validation will benefit the purpose in clock-gating-based low-power design. / Ph. D.

Driver violations at traffic signals are a major cause of intersection vehicle crashes. The yellow interval is used to inform approaching drivers of an upcoming change in the traffic signal indication from green to red. Current yellow-interval durations are currently calculated to accommodate for dilemma zone protection for passenger cars only. Buses with different vehicle, driver, and occupancy characteristics behave differently at the onset of a yellow indication. The research presented in this thesis characterizes the difference between bus and passenger car driver behavior at the onset of yellow-indication. A revised set of yellow timing procedures are presented to address the requirements for bus dilemma zone protection. A dataset of 864 stop-go records were collected as part of the research effort using a school bus approaching a traffic signal on the Virginia Smart Road facility. The experiment was conducted at an instructed speed limit of 57 km/h (35 mph) approach speed where participant drivers were presented with yellow indications. A total of 36 participating bus drivers were randomly selected from three age groups (under 40 years old, 40 to 64 years old and 65 and above) with equal number of male and female for each age group. Using the data collected as part of this research effort, statistical models were created to model bus driver perception-reaction times (PRTs) and deceleration levels considering driver attributes (age and gender), roadway grade, vehicle approach speed, and time to intersection (TTI) at the onset of the yellow indication. A Monte-Carlo simulation was conducted to develop appropriate yellow indication timings to provide adequate dilemma zone protection for buses. Lookup tables were then developed for different reliability levels to provide practical guidelines for the design of yellow signal timings to accommodate different bus percentages within the traffic stream. The recommended change durations can be integrated within the Vehicle Infrastructure Integration (VII) initiative to provide customizable driver warnings prior to a transition to a red indication. / Master of Science

Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, effective, and comprehensive technique for designers to estimate power and delay of a design operating in the Ultra-Low-Voltage region. While some frameworks and mathematical models exist to estimate power or delay, certain limitations exist, such as being applicable to either power or delay, or within a certain region of transistor operation. This thesis presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage all the way down into the subthreshold region. The framework uses the nominal frequency and power of a target circuit, which can be obtained using gate-level or transistor-level simulation tools as well as normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. A specific contribution of this thesis is to introduce a weighted average method, which is a major improvement to a previously published form of this framework. Another contribution is that the amount of process variation in ULV regions of a circuit can be estimated using the proposed framework. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite being many orders of magnitude lower than the nominal voltage, the errors are no greater than 11.27 percent for circuit delay, 16.96 percent for active energy, and 4.86 percent for leakage power for the weighted averages technique. This is in contrast to the original framework which has a maximum error of 39.75, 17.60, and 8.90 percent for circuit delay, active energy, and leakage power, respectively. To validate our framework, a detailed analysis is given in the presence of a variety of design parameters such as fanout, transistor widths, et cetera. In addition, we also validate our framework for a range of sequential benchmark circuits. / Master of Science

In this work, a simplified method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a dual 4-bit counter, was built using the library to demonstrate the suitability of the method. / Master of Science