由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。 / 為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局信息，我們使用類似ATPG 的算法產生狀態跳變使其能最大化已激活的路徑周圍的PSN影響。最後，基於近似電路的原理，我們提出了一種新的在線原位校正技術，即InTimeFix，用於糾正時序錯誤。由於實現近似電路的綜合僅需要簡單的電路結構分析，因此該技術能夠很容易的擴展到大型電路設計上去。 / With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and aging effects. In most cases, these reliability threats manifest themselves as timing errors on speed-paths (i.e., critical or near-critical paths) of the circuit. Embedding a large design guard band to prevent timing errors to occur is not an attractive solution, since this conservative design methodology diminishes the benefit of technology scaling. This creates several challenges on build a reliable systems, and the key problems include (i) how to optimize circuit’s timing performance with limited power budget for explosively increased potential speed-paths; (ii) how to generate high quality delay test pattern to capture ICs’ accurate worst-case delay; (iii) to have better power and performance tradeoff, we have to accept some infrequent timing errors in circuit’s the usage phase. Therefore, the question is how to achieve online timing error resilience. / To address the above issues, we first develop a novel technique to identify so-called false paths, which facilitate us to find much more false paths than conventional methods. By integrating our identified false paths into static timing analysis tool, we are able to achieve more accurate timing information and also save the cost used to optimize false paths. Then, due to the fact that existing delay automated test pattern generation (ATPG) methods may generate test patterns that are functionally-unreachable, and such patterns may incur excessive (or limited) power supply noise (PSN) on sensitized paths in test mode, thus leading to over-testing or under-testing of the circuits, we propose a novel pseudo-functional ATPG tool. By taking both circuit layout information and functional constrains into account, we use ATPG like algorithm to justify transitions that pose the maximized functional PSN effects on sensitized critical paths. Finally, we propose a novel in-situ correction technique to mask timing errors, namely InTimeFix, by introducing redundant approximation circuit with more timing slack for speed-paths into the design. The synthesis of the approximation circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Yuan, Feng. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 88-100). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Challenges to Solve Timing Uncertainty Problem --- p.2 / Chapter 1.2 --- Contributions and Thesis Outline --- p.5 / Chapter 2 --- Background --- p.7 / Chapter 2.1 --- Sources of Timing Uncertainty --- p.7 / Chapter 2.1.1 --- Process Variation --- p.7 / Chapter 2.1.2 --- Runtime Environment Fluctuation --- p.9 / Chapter 2.1.3 --- Aging Effect --- p.10 / Chapter 2.2 --- Technical Flow to Solve Timing Uncertainty Problem --- p.10 / Chapter 2.3 --- False Path --- p.12 / Chapter 2.3.1 --- Path Sensitization Criteria --- p.12 / Chapter 2.3.2 --- False Path Aware Timing Analysis --- p.13 / Chapter 2.4 --- Manufacturing Testing --- p.14 / Chapter 2.4.1 --- Functional Testing vs. Structural Testing --- p.14 / Chapter 2.4.2 --- Scan-Based DfT --- p.15 / Chapter 2.4.3 --- Pseudo-Functional Testing --- p.17 / Chapter 2.5 --- Timing Error Tolerance --- p.19 / Chapter 2.5.1 --- Timing Error Detection --- p.19 / Chapter 2.5.2 --- Timing Error Recover --- p.20 / Chapter 3 --- Timing-Independent False Path Identification --- p.23 / Chapter 3.1 --- Introduction --- p.23 / Chapter 3.2 --- Preliminaries and Motivation --- p.26 / Chapter 3.2.1 --- Motivation --- p.27 / Chapter 3.3 --- False Path Examination Considering Illegal States --- p.28 / Chapter 3.3.1 --- Path Sensitization Criterion --- p.28 / Chapter 3.3.2 --- Path-Aware Illegal State Identification --- p.30 / Chapter 3.3.3 --- Proposed Examination Procedure --- p.31 / Chapter 3.4 --- False Path Identification --- p.32 / Chapter 3.4.1 --- Overall Flow --- p.34 / Chapter 3.4.2 --- Static Implication Learning --- p.35 / Chapter 3.4.3 --- Suspicious Node Extraction --- p.36 / Chapter 3.4.4 --- S-Frontier Propagation --- p.37 / Chapter 3.5 --- Experimental Results --- p.38 / Chapter 3.6 --- Conclusion and Future Work --- p.42 / Chapter 4 --- PSN Aware Pseudo-Functional Delay Testing --- p.43 / Chapter 4.1 --- Introduction --- p.43 / Chapter 4.2 --- Preliminaries and Motivation --- p.45 / Chapter 4.2.1 --- Motivation --- p.46 / Chapter 4.3 --- Proposed Methodology --- p.48 / Chapter 4.4 --- Maximizing PSN Effects under Functional Constraints --- p.50 / Chapter 4.4.1 --- Pseudo-Functional Relevant Transitions Generation --- p.51 / Chapter 4.5 --- Experimental Results --- p.59 / Chapter 4.5.1 --- Experimental Setup --- p.59 / Chapter 4.5.2 --- Results and Discussion --- p.60 / Chapter 4.6 --- Conclusion --- p.64 / Chapter 5 --- In-Situ Timing Error Masking in Logic Circuits --- p.65 / Chapter 5.1 --- Introduction --- p.65 / Chapter 5.2 --- Prior Work and Motivation --- p.67 / Chapter 5.3 --- In-Situ Timing Error Masking with Approximate Logic --- p.69 / Chapter 5.3.1 --- Equivalent Circuit Construction with Approximate Logic --- p.70 / Chapter 5.3.2 --- Timing Error Masking with Approximate Logic --- p.72 / Chapter 5.4 --- Cost-Efficient Synthesis for InTimeFix --- p.75 / Chapter 5.4.1 --- Overall Flow --- p.76 / Chapter 5.4.2 --- Prime Critical Segment Extraction --- p.77 / Chapter 5.4.3 --- Prime Critical Segment Merging --- p.79 / Chapter 5.5 --- Experimental Results --- p.81 / Chapter 5.5.1 --- Experimental Setup --- p.81 / Chapter 5.5.2 --- Results and Discussion --- p.82 / Chapter 5.6 --- Conclusion --- p.85 / Chapter 6 --- Conclusion and Future Work --- p.86 / Bibliography --- p.100

Ferramentas de projeto de circuitos integrados (do inglˆes, electronic design automation, ou simplesmente EDA) tˆem um papel fundamental na crescente complexidade dos projetos de circuitos digitais. Elas permitem aos projetistas criar circuitos com um n´umero de componentes ordens de grandezas maior do que seria poss´ıvel se os circuitos fossem projetados `a m˜ao como nos dias iniciais da microeletrˆonica. Neste trabalho, dois importantes problemas em EDA ser˜ao abordados: dimensionamento de portas e posicionamento detalhado dirigido a desempenho. Para dimensionamento de portas, uma nova metodologia de relaxac¸ ˜ao Lagrangiana ´e apresentada baseada em informac¸ ˜ao de temporarizac¸ ˜ao locais e propagac¸ ˜ao de sensitividades. Para posicionamento detalhado dirigido a desempenho, um conjunto de movimentos de c´elulas ´e criado usando uma formac¸ ˜ao ´otima atenta `a forc¸a de alimentac¸ ˜ao para o balanceamento de cargas. Nossos resultados experimentais mostram que tais t´ecnicas s˜ao capazes de melhorar o atual estado-da-arte. / Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it would be possible by designing circuits by hand as was done in the early days of microelectronics. In this work, two important EDA problems are addressed: gate sizing and timing-driven detailed placement. They are studied and new techniques developed. For gate sizing, a new Lagrangian-relaxation methodology is presented based on local timing information and sensitivity propagation. For timing-driven detailed placement, a set of cell movement methods are created using drive strength-aware optimal formulation to driver/sink load balancing. Our experimental results shows that those techniques are able to improve the current state-of-the-art.

O dimensionamento da tecnologia trouxe consequências indesejáveis para manter a taxa de crescimento exponencial e levanta questões importantes relacionadas com a confiabilidade e robustez dos sistemas eletrônicos. Atualmente, microprocessadores modernos de superpipeline normalmente contêm milhões de dispositivos com cargas nos nós cada vez menores. Esse fator faz com que os circuitos sejam mais sensíveis a variabilidade ambiental e aumenta a probabilidade de um erro transiente acontecer. Erros transientes em circuitos sequenciais ocorrem quando uma única partícula energizada deposita carga suficiente perto de uma região sensível. Flip-Flops mestreescravo são os circuitos sequencias mais utilizados em projeto VLSI para armazenamento de dados. Se um bit-flip ocorrer dentro deles, eles perdem a informação prévia armazenada e podem causar um funcionamento incorreto do sistema. A fim de proporcionar sistemas mais confiáveis que possam lidar com os efeitos da radiação, este trabalho analisa o Fator de Vulnerabilidade Temporal (Timing Vulnerability Factor - TVF) em algumas topologias de flip-flops mestre-escravo em estágios de pipeline sob diferentes condições de operação. A janela de tempo efetivo que o bit-flip ainda pode ser capturado pelo próximo estágio é definido com janela de vulnerabilidade (WOV). O TVF corresponde ao tempo que o flip-flop é vulnerável a erros transientes induzidos pela radiação de acordo com a WOV e a frequência de operação. A primeira etapa deste trabalho determina a dependência entre o TVF com a propagação de falhas até o próximo estágio através de uma lógica combinacional com diferentes atrasos de propagação e com diferentes modelos de tecnologia, incluindo também as versões de alto desempenho e baixo consumo. Todas as simulações foram feitas sob as condições normais pré-definidas nos arquivos de tecnologia. Como a variabilidade se manifesta com o aumento ou diminuição das especificações iniciais, onde o principal problema é a incerteza sobre o valor armazenado em circuitos sequenciais, a segunda etapa deste trabalho consiste em avaliar o impacto que os efeitos da variabilidade ambiental causam no TVF. Algumas simulações foram refeitas considerando variações na tensão de alimentação e na temperatura em diferentes topologias e configurações de flip-flops mestre-escravo. Para encontrar os melhores resultados, é necessário tentar diminuir os valores de TVF, pois isso significa que eles serão menos vulneráveis a bit-flips. Atrasos de propagação entre dois circuitos sequenciais e frequências de operação mais altas ajudam a reduzir o TVF. Além disso, estas informações podem ser facilmente integradas em ferramentas de EDA para ajudar a identificar os flip-flops mestre-escravo mais vulneráveis antes de mitigar ou substituí-los por aqueles tolerantes a radiação. / Technology scaling has brought undesirable issues to maintain the exponential growth rate and it raises important topics related to reliability and robustness of electronic systems. Currently, modern super pipelined microprocessors typically contain many millions of devices with ever decreasing load capacitances. This factor makes circuits more sensitive to environmental variations and it is increased the probability to induce a soft error. Soft errors in sequential circuits occur when a single energetic particle deposits enough charge near a sensitive node. Master-slave flip-flops are the most adopted sequential elements to work as registers in pipeline and finite state machines. If a bit-flip happens inside them, they lose the previous stored information and may cause an incorrect system operation. To provide reliable systems that can cope with radiation effects, this work analysis the Timing Vulnerability Factor (TVF) of some master-slave D flip-flops topologies in pipeline stages under different operating conditions. The effective time window, which the bit-flip can still be captured by the next stage, is defined as Window of Vulnerability (WOV). TVF corresponds to the time that a flip-flop is vulnerable to radiation-induced soft errors according to WOV and clock frequency. In the first step of this work, it is determined the dependence between the TVF with the fault propagation to the next stage through a combinational logic with different propagation delays and with different nanometer technological models, including also high performance and low power versions. All these simulations were made under the pre-defined nominal conditions in technology files. The variability manifests with an increase or decreases to initial specification, where the main problem is the uncertainty about the value stored in sequential. In this way, the second step of this work evaluates the impact that environmental variability effect causes in TVF. Some simulations were redone considering supply voltage and temperature variations in different master-slave D flip-flop topologies configurations. To achieve better results, it is necessary to try to decrease the TVF values to reduce the vulnerability to bit-flips. The propagation delay between two sequential elements and higher clock frequencies collaborates to reduce TVF values. Moreover, all the information can be easily integrated into Electronic Design Automation (EDA) tools to help identifying the most vulnerable master-slave flip-flops before mitigating or replacing them by radiation hardened ones.

abstract: Timing performance is sensitive to fluctuations in time and motivation, thus interval timing and motivation are either inseparable or conflated processes. A behavioral systems model (e.g., Timberlake, 2000) of timing performance (Chapter 1) suggests that timing performance in externally-initiated (EI) procedures conflates behavioral modes differentially sensitive to motivation, but that response-initiated (RI) procedures potentially dissociate these behavioral modes. That is, timing performance in RI procedures is expected to not conflate these behavioral modes. According to the discriminative RI hypothesis, as initiating-responses become progressively discriminable from target responses, initiating-responses increasingly dissociate interval timing and motivation. Rats were trained in timing procedures in which a switch from a Short to a Long interval indexes timing performance (a latency-to-switch, LTS), and were then challenged with pre-feeding and extinction probes. In experiments 1 (Chapter 2) and 2 (Chapter 3), discriminability of initiating-responses was varied as a function of time, location, and form for rats trained in a switch-timing procedure. In experiment 3 (Chapter 4), the generalizability of the discriminative RI hypothesis was evaluated in rats trained in a temporal bisection procedure. In experiment 3, but not 1 and 2, RI enhanced temporal control of LTSs relative to EI. In experiments 1 and 2, the robustness of LTS medians to pre-feeding but not extinction increased with the discriminability of initiating-responses from target responses. In experiment 3, the mean LTS was robust to pre-feeding in EI and RI. In all three experiments, pre-feeding increased LTS variability in EI and RI. These results provide moderate support for the discriminative RI hypothesis, indicating that initiating-responses selectively and partially dissociate interval timing and motivation processes. Implications for the study of cognition and motivation processes are discussed (Chapter 5). / Dissertation/Thesis / Doctoral Dissertation Psychology 2018

Measuring the Effect of the Timing of First Birth on Mothers' Wages in the Czech Republic Magdalena Hummelová December 31, 2018 Abstract This thesis investigates the effect of fertility timing on women's long- run wages. Following the work of Herr (2016), by considering fertility timing in terms of labour market experience at the first birth, we study the effect on wages observed in the window 15 to 20 years after the labour market entry. This allows us to build different models for two groups of mothers: those entering the labour force with and without a child. We come to the conclusion that there is no effect of fertility timing for women entering the labour force already having a child. For women entering the labour force childless, the estimated postponement effect differs depending on whether they have an earning partner or not. If they do, there is clear cost of fertility delay by one more year (contrary to expectations) associated with a decrease in wages by 1%. This finding is very likely connected to a trend of lengthy parental leaves in the Czech Republic. If a woman does not have a partner, we observe an insignificant effect of first birth delay, yet positive. Comparing the results for women living in versus out of Prague, we see no significant difference in the effects.

Tian, Haitong. / Chinese abstract is on unnumbered page. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 65-74). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Our Contributions --- p.2 / Chapter 1.3 --- Organization of the Thesis --- p.3 / Chapter 2 --- Background Study --- p.4 / Chapter 2.1 --- Traditional Clock Routing Problem --- p.4 / Chapter 2.2 --- Tree-Based Clock Routing Algorithms --- p.5 / Chapter 2.2.1 --- Clock Routing Using H-tree --- p.5 / Chapter 2.2.2 --- Method of Means and Medians(MMM) --- p.6 / Chapter 2.2.3 --- Geometric Matching Algorithm (GMA) --- p.8 / Chapter 2.2.4 --- Exact Zero-Skew Algorithm --- p.9 / Chapter 2.2.5 --- Deferred Merge Embedding (DME) --- p.10 / Chapter 2.2.6 --- Boundary Merging and Embedding (BME) Algorithm --- p.14 / Chapter 2.2.7 --- Planar Clock Routing Algorithm --- p.17 / Chapter 2.2.8 --- Useful-skew Tree Algorithm --- p.18 / Chapter 2.3 --- Non-Tree Clock Distribution Networks --- p.19 / Chapter 2.3.1 --- Grid (Mesh) Structure --- p.20 / Chapter 2.3.2 --- Spine Structure --- p.20 / Chapter 2.3.3 --- Hybrid Structure --- p.21 / Chapter 2.4 --- Post-grid Clock Routing Problem --- p.22 / Chapter 2.5 --- Limitations of the Previous Work --- p.24 / Chapter 3 --- Post-Grid Clock Routing Problem --- p.26 / Chapter 3.1 --- Introduction --- p.26 / Chapter 3.2 --- Problem Definition --- p.27 / Chapter 3.3 --- Our Approach --- p.30 / Chapter 3.3.1 --- Delay-driven Path Expansion Algorithm --- p.31 / Chapter 3.3.2 --- Pre-processing to Connect Critical ports --- p.34 / Chapter 3.3.3 --- Post-processing to Reduce Capacitance --- p.36 / Chapter 3.4 --- Experimental Results --- p.39 / Chapter 3.4.1 --- Experiment Setup --- p.39 / Chapter 3.4.2 --- Validations of the Delay and Slew Estimation --- p.39 / Chapter 3.4.3 --- Comparisons with the Tree Grow (TG) Approach --- p.41 / Chapter 3.4.4 --- Lowest Achievable Delays --- p.42 / Chapter 3.4.5 --- Simulation Results --- p.42 / Chapter 4 --- Non-tree Based Post-Grid Clock Routing Problem --- p.44 / Chapter 4.1 --- Introduction --- p.44 / Chapter 4.2 --- Handling Ports with Large Load Capacitances --- p.46 / Chapter 4.2.1 --- Problem Ports Identification --- p.47 / Chapter 4.2.2 --- Non-Tree Construction --- p.47 / Chapter 4.2.3 --- Wire Link Selection --- p.48 / Chapter 4.3 --- Path Expansion in Non-tree Algorithm --- p.51 / Chapter 4.4 --- Limitations of the Non-tree Algorithm --- p.51 / Chapter 4.5 --- Experimental Results --- p.51 / Chapter 4.5.1 --- Experiment Setup --- p.51 / Chapter 4.5.2 --- Validations of the Delay and Slew Estimation --- p.52 / Chapter 4.5.3 --- Lowest Achievable Delays --- p.53 / Chapter 4.5.4 --- Results on New Benchmarks --- p.53 / Chapter 4.5.5 --- Simulation Results --- p.55 / Chapter 5 --- Efficient Partitioning-based Extension --- p.57 / Chapter 5.1 --- Introduction --- p.57 / Chapter 5.2 --- Partition-based Extension --- p.58 / Chapter 5.3 --- Experimental Results --- p.61 / Chapter 5.3.1 --- Experiment Setup --- p.61 / Chapter 5.3.2 --- Running Time Improvement with Partitioning Technique --- p.61 / Chapter 6 --- Conclusion --- p.63 / Bibliography --- p.65

abstract: Temporal bisection is a common procedure for the study of interval timing in humans and non-human animals, in which participants are trained to discriminate between a “short” and a “long” interval of time. Following stable and accurate discrimination, unreinforced probe intervals between the two values are tested. In temporal bisection studies, intermediate non-reinforced probe intervals are typically arithmetically- or geometrically- spaced, yielding point of subjective equality at the arithmetic and geometric mean of the trained anchor intervals. Brown et al. (2005) suggest that judgement of the length of an interval, even when not reinforced, is influenced by its subjective length in comparison to that of other intervals. This hypothesis predicts that skewing the distribution of probe intervals shifts the psychophysical function relating interval length to the probability of reporting that interval as “long.” Data from the present temporal bisection study, using rats, suggest that there may be a within-session shift in temporal bisection responding which accounts for observed shifts in the psychophysical functions, and that this may also influence how rats categorize ambiguous intervals. / Dissertation/Thesis / Masters Thesis Psychology 2019

This thesis presents two essays that explore firms’ incentive to share information in a multi-period decentralized supply chain and between competing firms. In the first essay, we consider a two-period supply chain in which one manufacturer supplies to a retailer. The retailer possesses some private demand information about the uncertain demand and decides whether to share the information with manufacturer. If an information sharing agreement is achieved, the retailer will share the observed demand information truthfully to the manufacturer. Then the selling season with two periods starts. In each period, the manufacturer decides on a wholesale price, which the retailer considers when deciding on the retail price. The manufacturer can observe the retailer's period-1 decision and the realized period-1 demand, and use this information when making the period-2 wholesale price decision. Thus, without information sharing, the two firms play a two-period signaling game. We find that voluntary information sharing is not possible because it benefits the manufacturer but hurts the retailer. However, different from one-period model, in which no information sharing can be achieved even with side payment, the manufacturer can make a side payment to the retailer to induce information sharing when the demand range is small. Both firms benefit from more accurate information regardless whether the retailer shares information. We also extend the two-period model to three-period model and infinite-period model, we find that the above results are robust. The second essay studies the incentives for information sharing between two competing firms with different production timing strategies. Each firm is planning to produce a new (upgraded) product. One firm adopts routine timing, whereby her production time is fixed according to her tradition of similar or previous models of the product. The other firm uses strategic timing, whereby his production time can be strategically chosen: be it before, simultaneously with, and after the routine firm. The two firms simultaneously choose whether or not to disclose their private demand information, make their quantity decisions based on any demand information available, and then compete in the market. We find that when the demand uncertainty is not high, both firms sharing information is the unique equilibrium outcome. Exactly one firm (the routine firm) sharing information can arise in equilibrium when the demand uncertainty is intermediate. These results are in stark contrast to extant literature which has shown that, for Cournot competitors with substitutable goods, no firm is willing to share demand information. Production timing is thus identified as a key driving force for horizontal information sharing, which might have been overlooked before. Surprisingly, when the competition becomes more intense, firms are more willing to share information. It is the information asymmetry that fundamentally change the strategic firm’s timing. We highlight the impact of signaling demand information for an early-production firm on the timing strategies, under different information sharing arrangements.

Traffic simulation and signal timing optimization are classified in structure into two main categories: (i) Macroscopic or Microscopic; (ii) Deterministic or Stochastic. Performance of the optimized signal timing derived by any tool is influenced by the methodology used in how calculations are executed in a particular tool. In this study, the performance of the optimal signal timing plans developed by two of the most popular traffic analysis tools, HCS and Tru-Traffic, each of them has its inbuilt objective function(s) to optimize signal timing for intersection, is compared with an ideal and an existing timing plans (base case) for the area of study using the microsimulation software VISSIM. An urban arterial with 29 intersections and high traffic in Fort Lauderdale, Florida serves as the test bed. To eliminate unfair superiority in the results, all experiments were performed under identical geometry and traffic conditions in each tool. Comparison of the optimized plans is conducted on the basis of average delay, average stopped delay, average number of stops, number of vehicles completed trips, latent delay, and latent demand from the simulated vehicle network performance evaluation results in VISSIM. The results indicate that, overall, HCS with its overall delay objective and the Tru-Traffic programs produce signal timing with comparable quality that performed similar to the un-optimized base case for most of the performance measures. / Includes bibliography. / Thesis (M.S.)--Florida Atlantic University, 2019. / FAU Electronic Theses and Dissertations Collection

Signal retiming, or signal optimization process, has not changed much over the last few decades. Traditional procedures rely on low-resolution data and a low-fidelity modeling approach. Such developed signal timing plans always require a fine-tuning process for deployed signal plans in field, thus questioning the very benefits of signal optimization. New trends suggest the use of high-resolution data, which are not easily available. At the same time, many improvements could be made if the traditional signal retiming process was modified to include the use of medium-resolution data and high-fidelity modeling. This study covers such an approach, where a traditional retiming procedure is modified to utilize large medium-resolution data sets, high-fidelity simulation models, and powerful stochastic optimization to develop robust signal timing plans. The study covers a 28-intersection urban corridor in Southeastern Florida. Medium-resolution data are used to identify peak-hour, Day-Of-Year (DOY) representative volumes for major seasons. Both low-fidelity and high-fidelity models are developed and calibrated with high precision to match the field signal operations. Then, by using traditional and stochastic optimization tools, signal timing plans are developed and tested in microsimulation. The findings reveal shortcomings of the traditional approach. Signal timing plans developed from medium-resolution data and high-fidelity modeling approach reduce average delay by 5%-26%. Travel times on the corridor are usually reduced by up to 10.5%, and the final solution does not transfer delay on the other neighboring streets (illustrated through latent delay), which is also decreased by 10%-49% when compared with the traditional results. In general, the novel approach has shown a great potential. The next step should be field testing and validation. / Includes bibliography. / Thesis (M.S.)--Florida Atlantic University, 2019. / FAU Electronic Theses and Dissertations Collection