Ho, Man Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 60-64). / Abstracts in English and Chinese. / Abstract --- p.i / Chinese Abstract --- p.iii / Acknowledgement --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.3 / Chapter 1.3 --- Contributions --- p.4 / Chapter 1.4 --- Thesis Organization --- p.5 / Chapter 2 --- Background Study --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Architecture & Design Flows --- p.6 / Chapter 2.3 --- Summary --- p.11 / Chapter 3 --- Architecture --- p.14 / Chapter 3.1 --- Overview --- p.14 / Chapter 3.2 --- Fabric Architecture --- p.15 / Chapter 3.2.1 --- Programmable Layers --- p.15 / Chapter 3.2.2 --- Fabric Organization --- p.16 / Chapter 3.3 --- Logic Block Designs --- p.19 / Chapter 3.3.1 --- Lookup-table (LUT) Based Logic Block --- p.19 / Chapter 3.3.2 --- Static CMOS Style Logic Block --- p.22 / Chapter 3.4 --- Summary --- p.26 / Chapter 4 --- EDA Design Flow --- p.27 / Chapter 4.1 --- Overview --- p.27 / Chapter 4.2 --- Library Preparation --- p.27 / Chapter 4.3 --- Design Synthesis --- p.29 / Chapter 4.4 --- Fabric Creation & Design Mapping Flows --- p.30 / Chapter 4.5 --- Summary --- p.35 / Chapter 5 --- Experimental Results --- p.36 / Chapter 5.1 --- Benchmark Circuits Description --- p.36 / Chapter 5.2 --- Experiment Configurations --- p.37 / Chapter 5.2.1 --- Synthesis --- p.38 / Chapter 5.2.2 --- Placement & Routing --- p.39 / Chapter 5.3 --- Comparison Metrics --- p.40 / Chapter 5.4 --- Area & Critical Path Delay Comparisons --- p.41 / Chapter 5.5 --- Summary --- p.46 / Chapter 6 --- Prototypes Testing --- p.47 / Chapter 6.1 --- Overview --- p.47 / Chapter 6.2 --- Second Tape-out --- p.47 / Chapter 6.2.1 --- Sample Application --- p.48 / Chapter 6.2.2 --- Signoff preparations --- p.50 / Chapter 6.2.3 --- Results for Test unit --- p.51 / Chapter 6.2.4 --- Functional test of Peak unit --- p.52 / Chapter 6.3 --- Third Tape-out --- p.53 / Chapter 6.3.1 --- Test Results . --- p.54 / Chapter 7 --- Conclusion --- p.57 / Chapter 7.1 --- Future Works --- p.58 / Bibliography --- p.59

Chau, Chun Pong. / "August 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 67-71). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.4 / Chapter 1.3 --- Contribution --- p.4 / Chapter 1.4 --- Thesis Organization --- p.5 / Chapter 2 --- Background and Review --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Logic Cell Style and Mask Programmability --- p.6 / Chapter 2.3 --- CAD Tools Compatibility --- p.8 / Chapter 2.4 --- Summary --- p.9 / Chapter 3 --- Architectural Design --- p.11 / Chapter 3.1 --- Overview --- p.11 / Chapter 3.2 --- Programmable Layers --- p.12 / Chapter 3.3 --- Combinational Logics --- p.12 / Chapter 3.4 --- Sequential Logics --- p.19 / Chapter 3.5 --- Inter-cell Connections --- p.21 / Chapter 3.6 --- Hard Macros --- p.22 / Chapter 3.7 --- Summary --- p.22 / Chapter 4 --- Design Flow --- p.23 / Chapter 4.1 --- Overview --- p.23 / Chapter 4.2 --- Library Creation --- p.24 / Chapter 4.3 --- Synthesis --- p.30 / Chapter 4.4 --- Placement and Routing --- p.30 / Chapter 4.5 --- Static Timing Analysis --- p.34 / Chapter 4.6 --- Summary --- p.35 / Chapter 5 --- Experimental Results --- p.36 / Chapter 5.1 --- Benchmark Circuits Description --- p.36 / Chapter 5.2 --- Experiment Settings --- p.37 / Chapter 5.3 --- Ratio of Dedicated Elements --- p.42 / Chapter 5.4 --- Delay and Area Comparison --- p.49 / Chapter 5.5 --- Distributed Memories --- p.53 / Chapter 5.6 --- Summary --- p.54 / Chapter 6 --- Prototypes and Applications --- p.55 / Chapter 6.1 --- Overview --- p.55 / Chapter 6.2 --- First Prototype --- p.55 / Chapter 6.3 --- Second Prototype --- p.63 / Chapter 7 --- Conclusion --- p.65 / Chapter 7.1 --- Future Work --- p.66 / Chapter 7.2 --- Concluding Remark --- p.67

Thesis (Ph.D.)--McMaster University, 2005. / Supervisor: Nicola Nicolici. Includes bibliographical references (189-208 p.)

Modular exponentiation and modular multiplication are the most used operations in current cryptographic systems. Some well-known cryptographic algorithms, such as RSA, Diffie-Hellman key exchange, and DSA, require modular exponentiation operations. This is performed with a series of modular multiplications to the extent of its exponent in a certain fashion depending on the exponentiation algorithm used. Cryptographic functions are very likely to be applied in current applications that perform information exchange to secure, verify, or authenticate data. Most notable is the use of such applications in Internet based information exchange. Smart cards, hand-helds, cell phones and many other small devices also need to perform information exchange and are likely to apply cryptographic functions. A hardware solution to perform a cryptographic function is generally faster and more secure than a software solution. Thus, a fast and area efficient modular exponentiation hardware solution would provide a better infrastructure for current cryptographic techniques. In certain cryptographic algorithms, very large precisions are used. Further, the precision may vary. Most of the hardware designs for modular multiplication and modular exponentiation are fixed-precision solutions. A scalable Montgomery Multiplier (MM) to perform modular multiplication has been proposed and can operate on input values of any bit-size, but the maximum bit-size should be known and is the limiting factor. The multiplier can calculate any operand size less than the maximal precision. However, this design's parameters should be optimized depending on the operand precision for which the design is used. A software application was developed in C to find the optimized design for the scalable MM module. It performs area-time trade-off for the most commonly used precisions in order to obtain a fast and area efficient solution for the common case. A modular exponentiation system is developed using this scalable multiplier design. Since the multiplier can operate on any operand size up to a certain maximum value, the exponentiation system that utilizes the multiplier will inherit the same capability. This thesis work presents the design and implementation of an exponentiation algorithm in hardware utilizing the optimized scalable Montgomery Multiplier. The design uses a parallel exponentiation algorithm to reduce the total computation time. The modular exponentiation system experimental results are analyzed and compared with software and other hardware implementations. / Graduation date: 2002

Thesis (M Eng) -- University of South Australia, 1992

Thesis (M Eng) -- University of South Australia, 1992

Thesis (M.App.Sc.) - Carleton University, 2003. / Includes bibliographical references (p.94-97 ). Also available in electronic format on the Internet.

Thesis (Ph. D.)--University of Washington, 1998. / Includes bibliographical references (leaves [152]-159).

Thesis (doctoral)--University of Oulu, 2004. / Includes bibliographical references. Also available on the World Wide Web.

Thesis (Ph. D.)--Rutgers University, 2008. / "Graduate Program in Electrical and Computer Engineering." Includes bibliographical references (p. 101-106).