Thesis (M. Eng.)--Carleton University, 1993. / Also available in electronic format on the Internet.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / David E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第21975号 / 情博第703号 / 新制||情||121(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 佐藤 高史, 教授 小野寺 秀俊, 教授 岡部 寿男 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

The design of specialized instructions for application specific processors is a challenging task. This thesis describes the issues of effective specification and use of specialized instructions for optimization of applications. It focuses on improvements of the outputs and usability of the semiatomatic method of selection of specialized instructions to allow the optimization of complicated applications. This method combines manual selection of instructions by marking a section of source code in the application and automatic generation of the instruction description in the modelling language.

There is a seemingly endless miniaturization of electronic components, which has enabled designers to build sophisticated computing structureson silicon chips. Consequently, electronic systems are continuously improving with new and more advanced functionalities. Design complexity ofthese Systems on Chip (SoC) is reduced by the use of pre-designed cores. However, several problems related to the interconnection of coresremain. Network on Chip (NoC) is a new SoC design paradigm, which targets the interconnect problems using classical network concepts. Still,SoC cores show large variance in size and functionality, whereas several NoC benefits relate to regularity and homogeneity. This thesis studies some network aspects which are characteristic to NoC systems. One is the issue of area wastage in NoC due to cores of varioussizes. We elaborate on using oversized regions in regular mesh NoC and identify several new design possibilities. Adverse effects of regions oncommunication are outlined and evaluated by simulation. Deadlock freedom is an important region issue, since it affects both the usability and performance of routing algorithms. The concept of faultyblocks, used in deadlock free fault-tolerant routing algorithms has similarities with rectangular regions. We have improved and adopted one suchalgorithm to provide deadlock free routing in NoC with regions. This work also offers a methodology for designing topology agnostic, deadlockfree, highly adaptive application specific routing algorithms. The methodology exploits information about communication among tasks of anapplication. This is used in the analysis of deadlock freedom, such that fewer deadlock preventing routing restrictions are required. A comparative study of the two proposed routing algorithms shows that the application specific algorithm gives significantly higher performance.But, the fault-tolerant algorithm may be preferred for systems requiring support for general communication. Several extensions to our work areproposed, for example in areas such as core mapping and efficient routing algorithms. The region concept can be extended for supporting reuse ofa pre-designed NoC as a component in a larger hierarchical NoC.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第21769号 / 工博第4586号 / 新制||工||1715(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 小嶋 浩嗣, 准教授 海老原 祐輔, 准教授 三谷 友彦 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM

In this thesis, we present a versatile parallel programming model composed of an individual general-purpose processor aided by several application-specific coprocessors. These computing units operate under a simplification of the master-worker model. The user-defined coprocessors may be either homogeneous or heterogeneous. We analyze system performance with regard to system size and task granularity, and we present experimental results to determine the optimal operating conditions. Finally, we consider the suitability of this approach for scientific simulations — specifically for use in agent-based models of biological systems. / Master of Science

Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d’entretien de type Colpitts,la mise en forme et jusqu’à l’adaptation du signal à sa charge d’utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s’orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del’architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l’avons reportée par flip chip sur une interfacespécifique pour / The increasing demand for high-performance devices featuring compact, lighter-weight designs with low-power consumptionalso impacts quartz crystal oscillators used in metrological applications (time bases, sensors), telephony or navigation. Inthis context, we have developed an ASIC (Application Specific Integrated Circuit) in 0.35 μm SiGe BiCMOS technology(Austriamicrosystems®) supplied by 3.3 V (±10%) to realize a miniaturized quartz crystal oscillator operating in the 10 MHzto 100 MHz frequency range. The fabricated die hosts several RF cells in a 4 mm2 area, including a sustaining amplifier(Colpitts topology), a signal shaping circuit and an output buffer dedicated to a specific load (50 W or HCMOS). These cellsare biased by a fully integrated CMOS bandgap voltage reference. The die power consumption remains lower than 100 mWfor a targeted phase noise floor as low as −150 dBc/Hz at a 40 MHz carrier frequency. A thermal control loop has in additionbeen partially integrated to the ASIC, in order to reduce the quartz resonator thermal sensitivity as well as to extend thepotential application field of the developed die to oven applications (OCXO). The thermal control, that is strongly dependanton the mechanical design, has been designed and tested by using electrical analogy modeling on Spectre® simulator. Finallyour integrated circuit has been connected to a specific substrate using flip chip technology to realize a miniaturized quartzcrystal oscillator packaged on a TO-8 enclosure (Ø15.2 mm).

Cette thèse porte sur le développement d'un capteur de pixel monolithique CMOS utilisé pourl’identification et le comptage des particules ionisés dan l’espace avec un flux élevé. Un nouveauconcept pour l’identification de l’espèce des particules proposé dans la présente étude, est basésur l'analyse des amas de particules déclenchés. Pour valider ce nouveau concept, un capteur detaille complet, qui comprend la matrice de pixel sensible aux particules ionisés signal, une chaînede traitement du signal analogique, un convertisseur analogue numérique de 3 bits, et untraitement du signal numérique a été conçu dans un processus de 0.35 μm. Le capteur sortiedirectement des informations de flux à travers 4 canaux avec un débit de données très faible(80 bps) et dissipation d’énergie minimale (~ 100 mW). Chaque canal représente particules avecdifférentes espèces et les énergies. La densité maximum de flux mesurable est jusqu'à 108particules/cm2/s (coups s'accumulent < 5%). Un prototype à échelle réduite a été fabriqué et testéavec trois types d'illumination de rayonnement (rayons X, les électrons et laser infrarouge). Tousles résultats obtenus valident le nouveau concept proposé. Un moniteur de rayonnement spatialtrès miniaturisé basé sur un capteur de pixel CMOS peut être prévu. Le moniteur peut présente lesmêmes performances que les compteurs actuels, mais avec une dissipation de puissance réduited'un ordre de grandeur qu'un poids, un volume d'encombrement et un coût moindre. En outre, enraison de ses sorties de haut niveau et faible débit de données, aucune traitement supplémentairedu signal dehors du capteur est nécessaire, ce qui le rend particulièrement attrayant pour desapplications dan les petits satellitaires. / This thesis focuses on the development of a CMOS monolithic pixel sensor used for space ionizingparticles identification and counting in high flux. A new concept for single particle identification isproposed in this study, which is based on the analysis of particle triggered clusters. To validate thisnew concept, a full size sensor including the sensitive pixel matrix, an analogue signal processingchain, a 3-bit analogue to digital converter, and a digital processing stage was designed in a 0.35μm process. The sensor directly output particles flux information through 4 channels with a verylow data rate (80 bps) and minimal power dissipation (~ 100mW). Each channel representsparticles with different species and energies. The highest measurable flux density is up to 108particles/cm2/s (hits pile up < 5%). A reduced scale prototype was fabricated and tested with 3types of radiation illumination (X-ray, electrons and infrared laser). All the results obtained validatethe proposed new concept and a highly miniaturized space radiation monitor based on a singleCMOS pixel sensor could be foreseen. The monitor could provide measurements of comparable orbetter quality than existing instruments, but at around an order of magnitude lower powerconsumption, mass and volume and a lower unit cost. Moreover, due to its high level and low datarate outputs, no signal treatment power aside the sensor is required which makes it especiallyattractive for small satellite application.

<p>Routers are probably the most important component of a NoC, as the performance of the whole network is driven by the routers’ performance. Cost for the whole network in terms of area will also be minimised if the router design is kept small. A new application specific processor architecture for implementing NoC routers is proposed in this master thesis, which will be called µNP (Micro-Network Processor). The aim is to offer a solution in which there is a trade-off between the high performance of routers implemented in hardware and the high level of flexibility that could be achieved by loading a software that routed packets into a GPP. Therefore, a study including the design of a hardware based router and a GPP based router has been conducted. In this project the first version of the µNP has been designed and a complete instruction set, along with some sample programs, is also proposed. The results show that, in the best case for all implementation options, µNP was 7.5 times slower than the hardware based router. It has also behaved more than 100 times faster than the GPP based router, keeping almost the same degree of flexibility for routing purposes within NoC.</p>