The world of wireless communications is under constant change. Radio standards evolve and new standards emerge. More and more functionality is put into wireless terminals. E.g. mobile phones need to handle both second and third generation mobile telephony as well as Bluetooth, and will soon also support wireless LAN functionality, reception of digital audio and video broadcasting, etc. These developments have lead to an increased interest in software defined radio (SDR), i.e. radio devices that can be reconfigured via software. SDR would provide benefits such as low cost for multi-mode devices, reuse of the same hardware in different products, and increased product life time via software updates. One essential part of any software defined radio is a programmable baseband processor that is flexible enough to handle different types of modulation, different channel coding schemes, and different trade-offs between data rate and mobility. So far, programmable baseband solutions have mostly been used in high end systems such as mobile telephony base stations since the cost and power consumption have been considered too high for handheld terminals. In this work a new low power and low silicon area programmable baseband processor architecture aimed for multi-mode terminals is presented. The architecture is based on a customized DSP core and a number of hardware accelerators connected via a configurable network. The architecture offers a good tradeoff between flexibility and performance through an optimized instruction set, efficient hardware acceleration of carefully selected functions, low memory cost, and low control overhead. One main contribution of this work is a study of important issues in programmable baseband processing such as software-hardware partitioning, instruction level acceleration, low power design, and memory issues. Further contributions are a unique optimized instruction set architecture, a unique architecture for efficient integration of hardware accelerators in the processor, and mapping of complete baseband applications to the presented architecture. The architecture has been proven in a manufactured demonstrator chip for wireless LAN applications. Wireless LAN firmware has been developed and run on the chip at full speed. Silicon area and measured power consumption have proven to be similar to that of a non-programmable ASIC solution.

Advancement in cryptography over the past few decades has enabled a spectrum of security mechanisms and protocols for many applications. Despite the algorithmic security of classic cryptography, there are limitations in application and implementation of standard security methods in ultra-low energy and resource constrained systems. In addition, implementations of standard cryptographic methods can be prone to physical attacks that involve hardware level invasive or non-invasive attacks. Physical unclonable functions (PUFs) provide a complimentary security paradigm for a number of application spaces where classic cryptography has shown to be inefficient or inadequate for the above reasons. PUFs rely on intrinsic device-dependent physical variation at the microscopic scale. Physical variation results from imperfection and random fluctuations during the manufacturing process which impact each device’s characteristics in a unique way. PUFs at the circuit level amplify and capture variation in electrical characteristics to derive and establish a unique device-dependent challenge-response mapping. Prior to this work, PUF implementations were unsuitable for low power applications and vulnerable to wide range of security attacks. This doctoral thesis presents a coherent framework to derive formal requirements to design architectures and protocols for PUFs. To the best of our knowledge, this is the first comprehensive work that introduces and integrates these pieces together. The contributions include an introduction of structural requirements and metrics to classify and evaluate PUFs, design of novel architectures to fulfill these requirements, implementation and evaluation of the proposed architectures, and integration into real-world security protocols. First, I formally define and derive a new set of fundamental requirements and properties for PUFs. This work is the first attempt to provide structural requirements and guideline for design of PUF architectures. Moreover, a suite of statistical properties of PUF responses and metrics are introduced to evaluate PUFs. Second, using the proposed requirements, new and efficient PUF architectures are designed and implemented on both analog and digital platforms. In this work, the most power efficient and smallest PUF known to date is designed and implemented on ASICs that exploits analog variation in sub-threshold leakage currents of MOS devices. On the digital platform, the first successful implementation of Arbiter-PUF on FPGA was accomplished in this work after years of unsuccessful attempts by the research community. I introduced a programmable delay tuning mechanism with pico-second resolution which serves as a key component in implementation of the Arbiter-PUF on FPGA. Full performance analysis and comparison is carried out through comprehensive device simulations as well as measurements performed on a population of FPGA devices. Finally, I present the design of low-overhead and secure protocols using PUFs for integration in lightweight identification and authentication applications. The new protocols are designed with elegant simplicity to avoid the use of heavy hash operations or any error correction. The first protocol uses a time bound on the authentication process while second uses a pattern-matching index-based method to thwart reverseengineering and machine learning attacks. Using machine learning methods during the commissioning phase, a compact representation of PUF is derived and stored in a database for authentication.

The FPGA GPU architecture proposed in this thesis was motivated by underserved markets for graphics processing that desire flexibility, long-term device availability, scalability, certifiability, and high reliability. These markets of industrial, medical, and avionics applications often are forced to rely on the latest GPUs that were actually designed for gaming PCs or handheld consumer devices. The architecture for the GPU in this thesis was crafted specifically for an FPGA and therefore takes advantage of its capabilities while also avoiding its limitations. Previous work did not specifically exploit the FPGA's structures and instead used FPGA implementations merely as an integration platform prior to proceeding on to a final ASIC design. The target of an FPGA for this architecture is also important because its flexibility and programmability allow the GPU's performance to be scaled or supplemented to fit unique application requirements. This tailoring of the architecture to specific requirements minimizes power consumption and device cost while still satisfying performance, certification, and device availability requirements. To demonstrate the feasibility of the flexible FPGA GPU architectural concepts, the architecture is applied to an avionics application and analyzed to confirm satisfactory results. The architecture is further validated through the development of extensions to support more comprehensive graphics processing applications. In addition, the breadth of this research is illustrated through its applicability to general-purpose computations and more specifically, scientific visualizations.

Routers are probably the most important component of a NoC, as the performance of the whole network is driven by the routers’ performance. Cost for the whole network in terms of area will also be minimised if the router design is kept small. A new application specific processor architecture for implementing NoC routers is proposed in this master thesis, which will be called µNP (Micro-Network Processor). The aim is to offer a solution in which there is a trade-off between the high performance of routers implemented in hardware and the high level of flexibility that could be achieved by loading a software that routed packets into a GPP. Therefore, a study including the design of a hardware based router and a GPP based router has been conducted. In this project the first version of the µNP has been designed and a complete instruction set, along with some sample programs, is also proposed. The results show that, in the best case for all implementation options, µNP was 7.5 times slower than the hardware based router. It has also behaved more than 100 times faster than the GPP based router, keeping almost the same degree of flexibility for routing purposes within NoC.

The doctoral thesis deals with development and design of novel architectures of digital filters for low-power integrated circuits. The main goal was to achieve optimum parameters of digital filters with respect to the chip area, power consumption and operating frequency. The target group of the proposed architectures are application specific integrated circuits designed for signal processing from sensors using delta-sigma modulators. Three novel architectures of digital filters optimized for low-power integrated circuits are presented in the thesis. The thesis provides analysis and comparison of parameters of the new filter architectures with the parameters of architectures generated by Matlab tool. A software tool has been designed and developed for the practical application of the proposed architectures of digital filters. The developed software tool allows generating hardware description of the filters with respect to defined parameters.

Application specific instruction set processors become part of every day life although it's not always visible at first sight. During their development it's needed to somehow describe their architecture, instruction set and behavior. To make their developement worth, it's necessary to be able to create applications for these processors and during application development errors are always made. Debuggers serve to discover and help fixing them. This paper summarises some basic information to debugger development and describes implementation for processors created using the Lissom project.

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Thesis (D.Tech (Engineering Electrical)) - Central University of Technology, Free State, 2005 / When Thomas Edison invented his carbon filament lamp in 1879, gas shares fell overnight. A committee of inquiry was set up to examine the future possibilities of the new method of lighting, and had reached the conclusion that electric light in the home was fanciful and absurd. Today electric light burns in practically every house in the civilised world, with many great advances in the production and use of electricity and electric power supplied by various utilities. The objective of the electric utility to deliver pure sinusoidal voltage at fairly constant magnitude throughout their system is complicated by the fact that there are currently loads on the system that produce harmonic voltages, which result in distorted voltages and currents that can adversely impact on the system performance in different ways. Because the numbers of harmonic producing loads have increased over the years, it has become necessary to address their influence, when making any additions or changes to an installation. Quality of supply measurements have long been used to characterise non-linearity on the power system, and have traditionally been measured with expensive portable analysers. A potentially faster, more integrated, and more flexible solution to measure the harmonics with a Supervisory System is accomplished by this research. Any script which aspired to cover in full detail the whole field of a subject so enormous as techniques to measure the quality of electricity supply on a SCADA system, would hardly be practical in less than a few volumes. The pretensions of this research are both modest and of a more immediate value to the reader.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / GSFC in keeping with the tenets of NASA has been aggressively investigating new technologies for spacecraft and ground communications and processing. The application of these technologies, together with standardized telemetry formats, make it possible to build systems that provide high-performance at low cost in a short development cycle. The High Rate Telemetry Acquisition System (HRTAS) Prototype is one such effort that has validated Goddard's push towards faster, better and cheaper. The HRTAS system architecture is based on the Peripheral Component Interconnect (PCI) bus and VLSI Application-Specific Integrated Circuits (ASICs). These ASICs perform frame synchronization, bit-transition density decoding, cyclic redundancy code (CRC) error checking, Reed-Solomon error detection/correction, data unit sorting, packet extraction, annotation and other service processing. This processing in performed at rates of up to and greater than 150 Mbps sustained using a high-end performance workstation running standard UNIX O/S, (DEC 4100 with DEC UNIX or better). ASICs are also used for the digital reception of Intermediate Frequency (IF) telemetry as well as the spacecraft command interface for commands and data simulations. To improve the efficiency of the back-end processing, the level zero processing sorting element is being developed. This will provide a complete hardware solution to extracting and sorting source data units and making these available in separate files on a remote disk system. Research is on going to extend this development to higher levels of the science data processing pipeline. The fact that level 1 and higher processing is instrument dependent; an acceleration approach utilizing ASICs is not feasible. The advent of field programmable gate array (FPGA) based computing, referred to as adaptive or reconfigurable computing, provides a processing performance close to ASIC levels while maintaining much of the programmability of traditional microprocessor based systems. This adaptive computing paradigm has been successfully demonstrated and its cost performance validated, to make it a viable technology for the level one and higher processing element for the HRTAS. Higher levels of processing are defined as the extraction of useful information from source telemetry data. This information has to be made available to the science data user in a very short period of time. This paper will describe this low cost solution for high rate data processing at level one and higher processing levels. The paper will further discuss the cost-benefit of this technology in terms of cost, schedule, reliability and performance.

Les systèmes distribués supportent l'exécution d'un grand nombre d'applications pouvant avoir des contraintes d'exécution différentes. La sécurité pour ces systèmes possède une influence déterminante sur les performances et la qualité de service de ces applications. Le recours à la sécurité à base de politiques pour sécuriser ces systèmes est particulièrement attrayant. Toutefois, cette approche implique la spécification et le déploiement de politiques, qui reste une tâche laborieuse, souvent propice aux erreurs, et requiert une connaissance approfondie des mécanismes de sécurité. Dans cette thèse nous proposons un cadre pour la spécification, la vérification et l'implémentation des politiques pour la sécurité des systèmes distribués. Ce cadre repose sur un langage de spécification de politiques nommé PPL (Policy Programming Language) et une architecture de déploiement de politiques. Cette architecture se base sur le langage PPL et offre un support pour la compilation de politiques dans différents mécanismes d'implémentation en tenant compte des exigences de l'application ou du service sous-jacent. Elle permet par ailleurs une attribution automatique des politiques de sécurité aux composants d'implémentation. Le langage métier PPL fournit quant à lui des abstractions spécifiques pour permettre la spécification de politiques de sécurité facilitant ainsi leur développement et leur intégration dans le support de déploiement. Il est déclaratif, robuste, fortement expressif, et permet plusieurs possibilités de vérification. Il est aussi doté d'une sémantique formelle, qui permet de valider, vérifier et prouver les propriétés et les règles de sécurité d'une politique. / Distributed systems support the execution of a large number of applications that have different performance constraints. Security for these systems has a decisive influence on the performance and quality of service of such applications. The use of security-based policies to secure these systems is particularly attractive. However, this approach involves the specification and the deployment of policies, which remains a laborious task, often conducive to error, and requires a thorough knowledge of security mechanisms. In this thesis we propose a framework for specification, verification and implementation of security policies for distributed systems. This framework is based on a policy specification language called PPL (Policy Programming Language) and an architecture of policies deployment. This architecture is based on PPL language and offers a support for the compilation of policies in different mechanisms of implementation, taking into account the requirements of the application or the underlying service. It also enables automatic distribution of security policies to their implementation components. The PPL language provides specific abstractions to allow the specification of security policies and facilitating their development and integration in the deployment support. It is declarative, robust, highly expressive, and allows several possibilities of verification. It also has a formal semantic, which allows you to validate, verify and prove the properties of a security policy.