Zugl.: Kassel, Univ., Diss., 2009

Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (M.S.M.E.)--University of South Florida, 2003. / Title from PDF of title page. Document formatted into pages; contains 87 pages. Includes bibliographical references.

Thesis (M.S. in Physics)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Michael Melich, David Jenn, Rodney Johnson. Includes bibliographical references (p. 113-115). Also available online.

To overcome the issues of mobility degradation and charge trapping in silicon high-κ MOSFET, a stacked Y₂O₃(top)/HfO2(bottom) gate dielectric on silicon substrate has been developed. Compared to the HfO₂ reference, the new dielectric shows similar scalability, but superior channel mobility and device reliability. The mobility improvement can be attributed to reduced remote phonon scattering, which is associated with the smaller ionic polarization of Y₂O₃, and the suppressed coulomb scattering due to less electron trapping in the bulk of high-κ layer, and reduced metal impurities in the substrate. The passivation mechanisms for the silicon IPL passivation technique in GaAs/[alpha]-Si IPL/high-κ MOS system have been investigated. We demonstrate the [alpha]-Si IPL thickness dependence and substrate type dependence of interface state density (Dit) for GaAs MOS capacitors. The interface state density is strongly correlated to the thickness and quality of un-oxidized Si IPL and its interaction with the underlying substrate. The results can be explained by the models related to the quantum well narrowing or the reduced local trap density as the unoxidized Si IPL layer thickness decreases. By using optimal Si IPL thickness (~10 Å), GaAs MOS devices can achieve the same interface quality, as its silicon counterpart. Using Si IPL to unpin the surface Fermi level, the selfaligned depletion-mode and enhancement-mode GaAs n-MOSFETs are demonstrated. In addition, the charge trapping and wear-out characteristics of the GaAs/Si IPL/HfO2/TaN MOS devices are systematically investigated. High performance In0.53Ga0.47As nMOSFETs with Si IPL and HfO2 gate oxide have been demonstrated. We systematically investigate the impacts of 1) Source/Drain activation temperature, 2) post deposition annealing (PDA) temperature, 3) In[subscrip 0.53]Ga[subscript 0.47]As channel doping concentration, 4) channel thickness and 5) Si IPL thickness on the transistor performances. With the [mu]m, V[subscript d]=50 mV), drive current of 158 mA/mm (L[subscript g]=5 [mu]m, V[subscript gs]=V[subscript th]+2 V, V[subscript d]=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. optimal combination of these impacting factors, excellent device characteristics have been obtained, including the peak transconductance of 7.7 mS/mm (Lg=5 μm, Vd=50 mV), drive current of 158 mA/mm (Lg=5 [mu]m, Vgs=Vth+2 V, Vd=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. / text

The problem of heavy material and radiative losses in plasmonic devices has held back their implementation for compact and high-speed data storage and interconnects. One of the most interesting solutions to this problem currently under exploration is the addition of a gain material in close proximity to the metallic nanostructures for loss compensation. Here the physics of light transport in a nanoparticle array, and the operation of gain media in contact with the structure, are described and analytically modeled. A two-dimensional array of closely spaced gold nanoparticles has been fabricated by focused ion beam milling, and its electromagnetic response in the presence or absence of a dye coating has been simulated in preparation for pump-probe optical testing. The compensation of losses via a fluorophore coating has been proven for the first time in this geometry, for a physically realized sample. / text

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