Les circuits asynchrones se démarquent des circuits synchrones par une modularité quasi-parfaite, l'absence d'horloge, et le contrôle local. Ils tendent à constituer une sérieuse alternative pour pallier aux problèmes posés par l'intégration en silicium d'applications de plus en plus complexes. Le goulot d'étranglement principal pour l'adoption de la conception des circuits asynchrones se situe au niveau du manque de méthodologies et d'outils puissants pour ce type de conception. Ce travail de thèse porte sur la définition d'une méthodologie de conception de circuits intégrés asynchrones micropipeline. La synthèse micropipeline est une approche qui exploite à la fois les outils commerciaux de synthèse pour le chemin de données, et la synthèse de contrôleurs asynchrones pour le contrôle. La méthodologie générale pour la modélisation et la synthèse de circuits asynchrones est basée sur la spécification dite DTL (Data Transfer Level) qui définit une façon d'écrire les codes sources garantissant une synthèse rapide et systématique pouvant cibler plusieurs styles de circuits asynchrones. Cette méthode de conception part d'une spécification basée sur un langage de haut niveau (CHP ou Concurrent Hardware Processes). Elle permet en sortie de générer des circuits en portes logiques élémentaires et en portes de Muller. Il a été procédé à un prototypage de cette méthode de synthèse. Ce prototype est conçu pour être intégré dans l'outil de conception automatique de circuits asynchrones TAST (Tima Asynchronous Synthesis Tool) dont le synthétiseur génère des circuits asynchrones QDI, pour l'étendre à la génération de circuits micropipelines.

Les circuits asynchrones se caractérisent par l'absence d'horloge. Ils offrent des propriétés intéressantes pour l'intégration de systèmes dans les technologies submicroniques telles que robustesse, faible bruit, faible consommation, bonne modularité. Cependant, le manque de méthodes et outils de conception est un frein à leur développement. Les travaux présentés dans cette thèse portent sur la définition d'une méthodologie de conception de circuits intégrés asynchrones quasi-insensibles aux délais. Celle-ci permet d'une part la modélisation dans un langage de haut-niveau et la simulation dans un environnement standard et d'autre part la génération de circuits uniquement constitués de cellules standard. Cette méthodologie a été appliquée à l'étude et à la réalisation d'un processeur RISC 16-bit. Son architecture originale permet d'effectuer l'envoi des instructions dans l'ordre et de les terminer dans le désordre. Ce prototype fabriqué dans la technologie 0.25um de STMicroelectronics est l'un des processeurs asynchrones le plus rapide réalisé à ce jour

Concurrent systems, including asynchronous circuits, computer networks, and multi-threaded programs, have important applications, but they are also very complex and expensive to test. This thesis studies how to test concurrent systems through contexts consisting of queues. Queues, modeling buffers and communication delays, are an integral part of the test settings for concurrent systems. However, queues can also distort the behavior of the concurrent system as observed by the tester, so one should take into account the queues when defining conformance relations or deriving tests. On the other hand, queues can cause state explosion, so one should avoid testing them if they are reliable or have already been tested. To solve these problems, we propose two different solutions. The first solution is to derive tests using some test selection criteria such as test purposes, fault coverage, and transition coverage. The second solution is to compensate for the problems caused by the queues so that testers do not discern the presence of the queues in the first place. Unifying the presentation of the two solutions, we consider in a general testing framework partial specifications, various contexts, and a hierarchy of conformance relations. Case studies on test derivation for asynchronous circuits, communication protocols, and multi-threaded programs are presented to demonstrate the applications of the results.

Bibliography: leaves 216-224. / xix, 224 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis describes a collection of design techniques engineered for high speed operation. A new gate representation is proposed to better reflect their functionality in an asynchronous domain. Two microprocessors (ECSTAC and ECSCESS) are implemented as an illustration of these design techniques. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1998?

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 77-78). Also available in electronic format on the Internet.

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references. Also available in electronic format on the Internet.

Thesis (Ph.D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 180-186). Also available in electronic format on the Internet.

É contínua a procura por técnicas de construção de circuitos que ajudem a minimizar os problemas existentes no mercado de microeletrônica atual. Uma alternativa para a resolução destes problemas consiste na utilização de circuitos assíncronos. Circuitos aritméticos são alvo de um contínuo esforço na busca de melhores resultados de desempenho e área. Em especial o somador é uma das partes constituintes desta classe de circuitos que apresenta interessante campo para pesquisas. Este trabalho apresenta um método de avaliação de somadores implementados através do uso de famílias lógicas CMOS dual-rail. Esta tarefa é realizada através do uso de um circuito assíncrono que serve como base de avaliação. Este circuito obedece ao protocolo de comunicação utilizado pelos somadores e nele são desenvolvidas diversas aplicações para que seja possível avaliar o comportamento dos somadores quando expostos a diferentes padrões de vetores. Os parâmetros avaliados nas estruturas dos somadores são número de transistores, atraso e consumo de potência para topologias carry look-ahead e ripple carry adders. Na avaliação dos somadores através de simulação elétrica são utilizadas as ferramentas Pspice e Spectre da Cadence. As tecnologias utilizadas nesta caracterização são AMI 0.5 da MOSIS e AMS 0.35. Como resultados são apresentados dados que demonstram a economia no número de transistores obtida através do uso da técnica de múltiplas saídas para o CLA, que a família DCVS geralmente apresenta os menores atrasos médios quando comparada a outras estruturas e a potencialidade de famílias NCL. / The search for construction techniques of circuits that helps to minimize the challenges that occurs in nowadays microelectronic market is continuous. An alternative to solve great part of these problems is the use of asynchronous circuits. Arithmetic circuits are the target of a continuous effort in the pursuit of better results in terms of performance and area. Adder circuits in special compose a subset of this class of circuits that presents an interesting research field. This work presents an evaluation method for adders that where implemented through different dual-rail logic families. This task is accomplished through the use of asynchronous circuits used as an evaluation base. The asynchronous circuits implemented obey the communication protocol adopted by the adders and implement different applications. These applications are constructed with the finality of study the adder’s behavior when they are exposed to different vector patterns. The adder’s evaluated parameters are the number of transistors, delay and power consumption of topologies like Carry Look-ahead and Ripple Carry Adders. The electrical simulations were accomplished trough the use of Pspice and Cadence’s Spectre cad tools. MOSIS AMI 0.5 and AMS 0.35 transistor technologies were utilized in the electrical characterization of the adders. Some of the results obtained trough this work that could be cited are: the low transistor count presented for the Multiple Outputs CLA structures, the performance advantage of the DCVS family in relation to the other families and the evaluation of NCL logic family potentiality.

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.