In recent years, the automotive industry has been significantly affected by a number of challenges driven by globalisation, economic fluctuations, environmental awareness and rapid technological developments. As a consequence, product lifecycles are shortening and customer demands are becoming more diverse. To survive in such a business environment, manufacturers are striving to find a costeffective solution for fast and efficient development and reconfiguration of manufacturing systems to satisfy the needs of changing markets without losses in production. Production systems within automotive industry are vastly automated and heavily rely on PLC-based control systems. It has been established that one of the major obstacles in realising reconfigurable manufacturing systems is the fragmented engineering approach to implement control systems. Control engineering starts at a very late stage in the overall system engineering process and remains highly isolated from the mechanical design and build of the system. During this stage, control code is typically written manually in vendor-specific tools in a combination of IEC 61131-3 languages. Writing control code is a complex, time consuming and error-prone process.

The study of architectural parameterization has long neglected other parameterizations in favour of code selector descriptions. In this dissertation, we are concerned with providing linguistic notations for modelling architectures with special emphasis on translation. We focus on high level descriptions to aid code selection and storage allocation. The view taken in the thesis is that a description specializes a framework with a particular architecture. Independently, the framework must support other translation algorithms without constraining their freedom or forcing them towards architecture-specific idioms. The first contribution is an architectural description language with features tuned towards better parameterizability. Emphasis is laid on addressing site (compile time) parameterizability. Within the notation, the type system of the machine is decoupled from that of the language with the mapping being left to the user as a compile-time parameterization. This gives one more degree of freedom for the user to decide on the precision required based on the available realizations. We also give adequate representation to addressing modes. They are considered to be almost equivalent to operations in complexity. This makes the specification simpler for operations. From the framework's perspective, as a second contribution, we propose an algorithm for maintaining registers during allocation. Register allocation algorithms depend on the framework to inform them when registers are exhausted. In such a situation, we pro- pose an adaptation of bipartite graph matching to keep track of register usage during translation in the presence of architec- tural constraints. The research also aims at structuring both the specification and software to prevent the closed-syntax bottle- neck of a lot of specification languages. We also describe the architecture of the implementation in terms of a very flexible model called the blackboard model.

No mercado altamente globalizado de hoje, a manutenção dos equipamentos tem se tornado um fator crucial para as empresas dos mais diversos segmentos. Técnicas de manutenção baseadas no nível de degradação dos equipamentos estão sendo preferidas em detrimento das técnicas tradicionais como manutenção corretiva e preventiva, e trazem benefícios como tempos de paradas reduzidos, tarefas de manutenção facilitadas e melhor gerenciamento de ativos. Com o desenvolvimento das técnicas de manutenção inteligente, os sistemas embarcados que comportarão estes algoritmos necessitarão cada vez mais de alta flexibilidade, combinada com alta velocidade de processamento e baixo consumo. Em outras palavras, eles tornam-se cada vez mais complexos, o que tem impacto direto no projeto destes sistemas. Neste contexto, a programação baseada em modelos em conjunto com a capacidade de geração automática de código para uma dada plataforma tem despertado grande interesse. O presente trabalho tem como objetivo realizar a análise dos espaços de projeto e também do desempenho de diferentes implementações para algoritmos de manutenção inteligente quando executados em hardware e software. A partir de implementações disponíveis nos ambientes MATLAB e LabVIEW™ de um sistema de manutenção inteligente chamado Watchdog Agent™, e utilizando ferramentas de geração automática de código, o desempenho dos sistemas de manutenção gerados é comparado usando-se parâmetros como tempo de execução e ocupação de memória ou da área do FPGA. Para os testes são utilizados dados de vibração coletados de uma bancada de testes composta por um atuador eletromecânico para válvulas. / In today’s highly globalized market, equipment maintenance has become a crucial factor for companies from several segments. Maintenance strategies based on equipment’s condition level are being preferred in place of traditional techniques such as corrective and preventive maintenance, and incur in benefits such as reduced downtime, facilitated maintenance tasks and better assets management. With the development of intelligent maintenance techniques, the embedded systems that will be used with such algorithms will need increasingly more flexibility, combined with high processing speed and low power consumption. In other words, they became increasingly more complex, what directly impact in their project. Within this context, model based engineering associated with automatic platform-specific code generation capabilities are of great interest. This work has as objective to perform a design space exploration by analyzing the performance of different implementations for intelligent maintenance algorithms when executed in hardware and software. Based on implementations available in MATLAB™ and LabVIEW™ environments of an intelligent maintenance system called Watchdog Agent, and using automatic code generation tools, the performance of the generated systems are compared using parameters such as execution time and memory or FPGA area occupation. For the validation tests, vibration data collected from a test bench composed by an electric mechanical actuator will be used.

No mercado altamente globalizado de hoje, a manutenção dos equipamentos tem se tornado um fator crucial para as empresas dos mais diversos segmentos. Técnicas de manutenção baseadas no nível de degradação dos equipamentos estão sendo preferidas em detrimento das técnicas tradicionais como manutenção corretiva e preventiva, e trazem benefícios como tempos de paradas reduzidos, tarefas de manutenção facilitadas e melhor gerenciamento de ativos. Com o desenvolvimento das técnicas de manutenção inteligente, os sistemas embarcados que comportarão estes algoritmos necessitarão cada vez mais de alta flexibilidade, combinada com alta velocidade de processamento e baixo consumo. Em outras palavras, eles tornam-se cada vez mais complexos, o que tem impacto direto no projeto destes sistemas. Neste contexto, a programação baseada em modelos em conjunto com a capacidade de geração automática de código para uma dada plataforma tem despertado grande interesse. O presente trabalho tem como objetivo realizar a análise dos espaços de projeto e também do desempenho de diferentes implementações para algoritmos de manutenção inteligente quando executados em hardware e software. A partir de implementações disponíveis nos ambientes MATLAB e LabVIEW™ de um sistema de manutenção inteligente chamado Watchdog Agent™, e utilizando ferramentas de geração automática de código, o desempenho dos sistemas de manutenção gerados é comparado usando-se parâmetros como tempo de execução e ocupação de memória ou da área do FPGA. Para os testes são utilizados dados de vibração coletados de uma bancada de testes composta por um atuador eletromecânico para válvulas. / In today’s highly globalized market, equipment maintenance has become a crucial factor for companies from several segments. Maintenance strategies based on equipment’s condition level are being preferred in place of traditional techniques such as corrective and preventive maintenance, and incur in benefits such as reduced downtime, facilitated maintenance tasks and better assets management. With the development of intelligent maintenance techniques, the embedded systems that will be used with such algorithms will need increasingly more flexibility, combined with high processing speed and low power consumption. In other words, they became increasingly more complex, what directly impact in their project. Within this context, model based engineering associated with automatic platform-specific code generation capabilities are of great interest. This work has as objective to perform a design space exploration by analyzing the performance of different implementations for intelligent maintenance algorithms when executed in hardware and software. Based on implementations available in MATLAB™ and LabVIEW™ environments of an intelligent maintenance system called Watchdog Agent, and using automatic code generation tools, the performance of the generated systems are compared using parameters such as execution time and memory or FPGA area occupation. For the validation tests, vibration data collected from a test bench composed by an electric mechanical actuator will be used.

No mercado altamente globalizado de hoje, a manutenção dos equipamentos tem se tornado um fator crucial para as empresas dos mais diversos segmentos. Técnicas de manutenção baseadas no nível de degradação dos equipamentos estão sendo preferidas em detrimento das técnicas tradicionais como manutenção corretiva e preventiva, e trazem benefícios como tempos de paradas reduzidos, tarefas de manutenção facilitadas e melhor gerenciamento de ativos. Com o desenvolvimento das técnicas de manutenção inteligente, os sistemas embarcados que comportarão estes algoritmos necessitarão cada vez mais de alta flexibilidade, combinada com alta velocidade de processamento e baixo consumo. Em outras palavras, eles tornam-se cada vez mais complexos, o que tem impacto direto no projeto destes sistemas. Neste contexto, a programação baseada em modelos em conjunto com a capacidade de geração automática de código para uma dada plataforma tem despertado grande interesse. O presente trabalho tem como objetivo realizar a análise dos espaços de projeto e também do desempenho de diferentes implementações para algoritmos de manutenção inteligente quando executados em hardware e software. A partir de implementações disponíveis nos ambientes MATLAB e LabVIEW™ de um sistema de manutenção inteligente chamado Watchdog Agent™, e utilizando ferramentas de geração automática de código, o desempenho dos sistemas de manutenção gerados é comparado usando-se parâmetros como tempo de execução e ocupação de memória ou da área do FPGA. Para os testes são utilizados dados de vibração coletados de uma bancada de testes composta por um atuador eletromecânico para válvulas. / In today’s highly globalized market, equipment maintenance has become a crucial factor for companies from several segments. Maintenance strategies based on equipment’s condition level are being preferred in place of traditional techniques such as corrective and preventive maintenance, and incur in benefits such as reduced downtime, facilitated maintenance tasks and better assets management. With the development of intelligent maintenance techniques, the embedded systems that will be used with such algorithms will need increasingly more flexibility, combined with high processing speed and low power consumption. In other words, they became increasingly more complex, what directly impact in their project. Within this context, model based engineering associated with automatic platform-specific code generation capabilities are of great interest. This work has as objective to perform a design space exploration by analyzing the performance of different implementations for intelligent maintenance algorithms when executed in hardware and software. Based on implementations available in MATLAB™ and LabVIEW™ environments of an intelligent maintenance system called Watchdog Agent, and using automatic code generation tools, the performance of the generated systems are compared using parameters such as execution time and memory or FPGA area occupation. For the validation tests, vibration data collected from a test bench composed by an electric mechanical actuator will be used.

This research explores the Automation Interface created by Beckhoff through introducinga compiler solution. Today machine builders have to be able to build machinesor plants in different sizes and provide many variations of the machine orplant types. Automatic code generation can be used in the aspect to reuse code thathas been tested and is configurable to match the desired functionality. Additionally,the use of a pre-existing API could potentially result in less engineering resourceswasted in developing automatic code generation. This thesis aims to evaluate theAutomation Interface (AI) tool created by Beckhoff. This is accomplished throughmeans of incorporating the API functions into a compiler solution. The solution isdesigned to export the information required through an XML-file to generate PLCapplications.The generated PLC-code will be in Structured Text. In order to createa functional PLC-application, the construction of software requirements and testcases are established. The solution is then validated by means of generating a dataloggerto illustrate the usage. The exploratory research revealed both the benefitsand cons of using AI to a compiler solution. The evaluation indicated that the AutomationInterface can reduce engineering effort to produce a compiler solution, butthe learning curve of understanding the underlying components that work with theAPI required a great deal of effort.

A crescente demanda da indústria exige a produção de dispositivos embarcados em menos tempo e com mais funcionalidades diferentes. Isso implica diretamente no processo de desenvolvimento destes produtos requerendo novas técnicas para absorver a complexidade crescente dos projetos e para acelerar suas etapas de desenvolvimento. A linguagem UML vem sendo utilizada para absorver a complexidade do projeto de sistemas embarcados através de sua representação gráfica que torna o processo mais simples e intuitivo. Para acelerar o desenvolvimento surgiram processos que permitem, diretamente a partir modelos UML, a geração de código para linguagens de descrição de software embarcado (C, C++, Java) e para linguagens tradicionais de descrição de hardware (VHDL, Verilog). Diversos trabalhos e ferramentas comerciais foram desenvolvidos para automatizar o processo de geração de código convencional a partir de modelos UML (software). No entanto, pela complexidade da transformação existem apenas poucos trabalhos e nenhuma ferramenta comercial direcionado à geração de HDL a partir de UML, tornando este processo ainda pouco difundido. Nossa proposta é focada na geração de descrições de hardware na linguagem VHDL a partir de modelos UML de sistemas tempo-real embarcados (STRE), surgindo como alternativa ao processo de desenvolvimento de hardware. Apresenta uma metodologia completa para geração automática de código VHDL, permitindo que o comportamento descrito para o sistema modelado seja testado e validado antes de ser desenvolvido, acelerando o processo de produção de hardware e diminuindo as chances de erros de projeto. É proposto como um processo de engenharia dirigido por modelos (MDE) que cobre desde as fases de análise de requisitos e modelagem UML, até a geração de código fonte na linguagem VHDL, onde o foco é gerar na forma de descrições de hardware, todas aquelas funções lógicas de um sistema embarcado que normalmente são desenvolvidas em software. Para atingir este objetivo, foi desenvolvido neste trabalho um conjunto de regras de mapeamento que estende a funcionalidade da ferramenta GenERTiCA, utilizada como suporte ao processo. Adicionalmente, foram pesquisados e desenvolvidos conceitos que serviram como base para o desenvolvimento de regras utilizadas pela ferramenta suporte para guiar o processo de mapeamento entre as linguagens. Os conceitos e as regras propostas foram validados por meio de um estudo de caso, cujos resultados obtidos estão demonstrados nesta dissertação. / The growing market demand requires the production of embedded devices in less time and with more different features. This directly implies on the development process of these products requiring new techniques to absorb the growing complexity of projects and to accelerate their development stages. UML has been used to handle the embedded systems design complexity through its graphical representation that makes the process simpler and more intuitive. To speed up the development cycle, it has emerged some processes that permit code generating directly from UML models to embedded software description languages (C, C++, Java), and traditional hardware description languages (VHDL, Verilog). Several researches and commercial tools have been developed to automate the code generation process from UML models to conventional languages (software). However, due to the transformation complexity there are only few studies and no commercial tool addressed to HDL generation from UML models, making this process almost unknown. Our proposal is focused on generating hardware descriptions as VHDL code from UML models of real-time embedded systems (RTES), emerging as an alternative to the hardware development. It presents a complete methodology to the VHDL code generation, allowing the behavior described to the modeled system to be tested and validated before being implemented, accelerating the hardware production and decreasing the chances of design errors. It is proposed as a model-driven engineering (MDE) process that covers the phases of requirements analysis, UML modeling, models transformations, and the source code generating process to the VHDL language, where the focus is to generate as hardware descriptions all the logic functions of an embedded system which are usually developed as software. To achieve this goal, this work was developed a set of mapping rules which extends the functionality of the tool GenERTiCA, used to support the process. Additionally, it was researched and developed concepts that were the basis for the development of rules used by the tool support to guide the mapping process between languages. The concepts and proposed rules have been validated through a case study, whose results are shown in this dissertation.

This thesis proposes an approach for automatic code generation from a Colored Petri net specification. Two tools were developed for the aforementioned purpose, a Colored Petri net editor to create and modify Colored Petri nets, and an automatic code generator to generate code from a Colored Petri net specification. Through the use of the editor four models were created, these models were used as input to the automatic code generator. The automatic code generator successfully generated code from the Colored Petri net specification, code in the form of component scripts for the Unity3D game engine. However, the approach used by the code generator had flaws such as introducing overhead in the generated code, failing to deal with concurrency, and restricting the types of Colored Petri nets which could be used as input. The aforementioned tools could be used in the future to research the benefits and disadvantages of modeling game systems with Colored Petri nets, and automatically generating code from Colored Petri nets.

A crescente demanda da indústria exige a produção de dispositivos embarcados em menos tempo e com mais funcionalidades diferentes. Isso implica diretamente no processo de desenvolvimento destes produtos requerendo novas técnicas para absorver a complexidade crescente dos projetos e para acelerar suas etapas de desenvolvimento. A linguagem UML vem sendo utilizada para absorver a complexidade do projeto de sistemas embarcados através de sua representação gráfica que torna o processo mais simples e intuitivo. Para acelerar o desenvolvimento surgiram processos que permitem, diretamente a partir modelos UML, a geração de código para linguagens de descrição de software embarcado (C, C++, Java) e para linguagens tradicionais de descrição de hardware (VHDL, Verilog). Diversos trabalhos e ferramentas comerciais foram desenvolvidos para automatizar o processo de geração de código convencional a partir de modelos UML (software). No entanto, pela complexidade da transformação existem apenas poucos trabalhos e nenhuma ferramenta comercial direcionado à geração de HDL a partir de UML, tornando este processo ainda pouco difundido. Nossa proposta é focada na geração de descrições de hardware na linguagem VHDL a partir de modelos UML de sistemas tempo-real embarcados (STRE), surgindo como alternativa ao processo de desenvolvimento de hardware. Apresenta uma metodologia completa para geração automática de código VHDL, permitindo que o comportamento descrito para o sistema modelado seja testado e validado antes de ser desenvolvido, acelerando o processo de produção de hardware e diminuindo as chances de erros de projeto. É proposto como um processo de engenharia dirigido por modelos (MDE) que cobre desde as fases de análise de requisitos e modelagem UML, até a geração de código fonte na linguagem VHDL, onde o foco é gerar na forma de descrições de hardware, todas aquelas funções lógicas de um sistema embarcado que normalmente são desenvolvidas em software. Para atingir este objetivo, foi desenvolvido neste trabalho um conjunto de regras de mapeamento que estende a funcionalidade da ferramenta GenERTiCA, utilizada como suporte ao processo. Adicionalmente, foram pesquisados e desenvolvidos conceitos que serviram como base para o desenvolvimento de regras utilizadas pela ferramenta suporte para guiar o processo de mapeamento entre as linguagens. Os conceitos e as regras propostas foram validados por meio de um estudo de caso, cujos resultados obtidos estão demonstrados nesta dissertação. / The growing market demand requires the production of embedded devices in less time and with more different features. This directly implies on the development process of these products requiring new techniques to absorb the growing complexity of projects and to accelerate their development stages. UML has been used to handle the embedded systems design complexity through its graphical representation that makes the process simpler and more intuitive. To speed up the development cycle, it has emerged some processes that permit code generating directly from UML models to embedded software description languages (C, C++, Java), and traditional hardware description languages (VHDL, Verilog). Several researches and commercial tools have been developed to automate the code generation process from UML models to conventional languages (software). However, due to the transformation complexity there are only few studies and no commercial tool addressed to HDL generation from UML models, making this process almost unknown. Our proposal is focused on generating hardware descriptions as VHDL code from UML models of real-time embedded systems (RTES), emerging as an alternative to the hardware development. It presents a complete methodology to the VHDL code generation, allowing the behavior described to the modeled system to be tested and validated before being implemented, accelerating the hardware production and decreasing the chances of design errors. It is proposed as a model-driven engineering (MDE) process that covers the phases of requirements analysis, UML modeling, models transformations, and the source code generating process to the VHDL language, where the focus is to generate as hardware descriptions all the logic functions of an embedded system which are usually developed as software. To achieve this goal, this work was developed a set of mapping rules which extends the functionality of the tool GenERTiCA, used to support the process. Additionally, it was researched and developed concepts that were the basis for the development of rules used by the tool support to guide the mapping process between languages. The concepts and proposed rules have been validated through a case study, whose results are shown in this dissertation.

abstract: As the complexity of robotic systems and applications grows rapidly, development of high-performance, easy to use, and fully integrated development environments for those systems is inevitable. Model-Based Design (MBD) of dynamic systems using engineering software such as Simulink® from MathWorks®, SciCos from Metalau team and SystemModeler® from Wolfram® is quite popular nowadays. They provide tools for modeling, simulation, verification and in some cases automatic code generation for desktop applications, embedded systems and robots. For real-world implementation of models on the actual hardware, those models should be converted into compilable machine code either manually or automatically. Due to the complexity of robotic systems, manual code translation from model to code is not a feasible optimal solution so we need to move towards automated code generation for such systems. MathWorks® offers code generation facilities called Coder® products for this purpose. However in order to fully exploit the power of model-based design and code generation tools for robotic applications, we need to enhance those software systems by adding and modifying toolboxes, files and other artifacts as well as developing guidelines and procedures. In this thesis, an effort has been made to propose a guideline as well as a Simulink® library, StateFlow® interface API and a C/C++ interface API to complete this toolchain for NAO humanoid robots. Thus the model of the hierarchical control architecture can be easily and properly converted to code and built for implementation. / Dissertation/Thesis / M.S. Computer Science 2013