This master's thesis deals with designing and implementation of universal programmer with JTAG interface. The project consists of a hardware and software part. Theoretical part discusses actual state in using the standards for programming and testing electronic devices, with special emphasis on JTAG implementation. Next part deals with programming ARM and FPGA devices through JTAG. The programming of this devices using available software is described in the practical part of this document. Final product of this work is the programmer itself. The programmer consists of the hardware and supplement software. At the end of this thesis there is a conclusion about possible improvements and development in the future.

De part leur capacité de reconfiguration et les performances qu’ils offrent, les FPGAs sont de bons candidats pour accélérer des applications dans le Cloud. Cependant, les FPGAs présentent certaines caractéristiques qui font obstacle à leur utilisation dans le Cloud et leur adoption par les clients : premièrement, la programmation des FPGAs se fait à bas niveau et demande une certaine expertise, que n’ont pas nécessairement les clients habituels du Cloud. Deuxièmement, les FPGAs ne présentent pas de mécanismes natifs permettant leur intégration dans le modèle de gestion dynamique d’une infrastructure Cloud.Dans ce travail, nous proposons d’utiliser des architectures overlay afin de faciliter l’adoption, l’intégration et l’exploitation de FPGAs dans le Cloud. Les overlays sont des architectures reconfigurables elles-mêmes implémentée sur FPGA. En tant que couche d’abstraction matérielle placée entre le FPGA et les applications, les overlays permettent de monter le niveau d’abstraction du modèle d’exécution présenté aux applications et aux utilisateurs, ainsi que d’implémenter des mécanismes facilitant leur intégration et leur exploitation dans une infrastructure Cloud.Ce travail présente une approche verticale adressant tous les aspects de la mise en œuvre d’overlays dans le Cloud en tant qu’accélérateurs reconfigurables par les clients : de la conception et l’implémentation des overlays, leur intégration sur des plateformes FPGA commerciales, la mise en place de leurs mécanismes d’exploitation, jusqu’à la réalisationde leurs outils de programmation. L’environnement réalisé est complet, modulaire et extensible, il repose en partie sur différents outils existants, et démontre la faisabilité de notre approche. / Due to their reconfigurable capability and the performance they offer, FPGAs are good candidates for accelerating applications in the cloud. However, FPGAs have some features that hinder their use in the Cloud as well as their adoption by customers : first, FPGA programming is done at low level and requires some expertise that usual Cloud clients do not necessarily have. Secondly, FPGAs do not have native mechanisms allowing them to easily fit in the dynamic execution model of the Cloud.In this work, we propose to use overlay architectures to facilitate FPGA adoption, integration, and operation in the Cloud. Overlays are reconfigurable architectures synthesized on FPGA. As hardware abstraction layers placed between the FPGA and applications, overlays allow to raise the abstraction level of the execution model presented to applications and users, as well as to implement mechanisms making them fit in a Cloud infrastructure.This work presents a vertical approach addressing all aspects of overlay operation in the Cloud as reconfigurable accelerators programmable by tenants : from designing and implementing overlays, integrating them on commercial FPGA platforms, setting up their operating mechanisms, to developping their programming tools. The environment developped in this work is complete, modular and extensible, it is partially based on several existing tools, and demonstrate the feasibility of our approach.

Field Programmable Gate Arrays (FPGAs) are being used more frequently in space applications because of their reconfigurability and intensive processing capabilities. FPGAs in environments like space are susceptible to ionizing radiation which can cause Single Event Upsets (SEUs) in the FPGA's configuration memory. These upsets may cause the programmed user design on the FPGA to deviate from its normal behavior. Space missions cannot afford to allow important data processing applications to become corrupted due to these radiation upsets.Configuration scrubbing is an upset mitigation technique that detects and corrects upsets in an FPGA's configuration memory. Configuration scrubbing periodically monitors an FPGA's configuration memory utilizing mechanisms such as Error Correction Codes (ECCs), Cyclic Redundancy Checks (CRCs), a protected golden file, and partial reconfiguration to detect and correct upset memory bits. This work presents improved Xilinx 7-Series configuration scrubbing architectures that achieve minimal hardware footprints, competitive performance metrics, and robust detection and correction capabilities. The two principal scrubbing architectures presented in this work are the readback and hybrid scrubbers which detect and correct Single Bit Upsets (SBUs) and Multi-Bit Upsets (MBUs). Harnessing the performance advantages granted by the 7-Series internal Readback CRC scan, a hybrid scrubber built in software for the Zynq XZC07020 FPGA has been measured to correct SBUs in 8.024 ms, even-numbered MBUs in 13.38 ms, and odd-numbered MBUs in 21.40 ms. It can also perform a full readback scrub of the entire device in under two seconds. These scrubbing architectures were validated in radiation beam tests, where one of the architectures corrected MBUs as large as sixteen bits in a single frame.

The cellular operators (Vodacom, Cell C, MTN and now Virgin Mobile) market has over 39-million mobile phone subscribers and the fixed operator (Telkom) has almost 5 million subscribers [13]. Although the telecommunication sector has been experiencing this significant growth (in terms of numbers), monopolisation of the local loop by Telkom has also resulted in communication prices that are not affordable to the majority of South Africans. The government of South Africa has identified cost of telecommunication services as one of the key initiatives that must be addressed to improve equal levels of access to ICT services in general. Local Loop Unbundling (or LLU for short) has been identified by the South African government as a tool that will minimise control that Telkom has over the copper cable connecting exchanges to customers whilst at the same time driving down the costs of Telecommunication in the country. Although some countries have successfully implemented local loop unbundling, some have not been so successful [3]. This dissertation proposes ICT Systems and processes South Africa needs to have in place to become one of the few success stories. The proposed model was validated against the different models adopted in countries like France, Portugal, United Kingdom and Austria. This dissertation develops a model for implementing local loop unbundling in the South African ICT sector. Local loop unbundling (in short LLU) has been successfully (and unsuccessfully) implemented in a number of countries around the world [3]. The model being proposed recommends best practices to be followed by all stakeholders to ensure successful deployment of local loop unbundling. The research takes a closer look at the South African ICT sector and makes recommendations on processes and systems that are necessary to ensure successful deployment of local loop unbundling in South Africa. The dissertation is written from the view of Telkom (The incumbent Operator), competitors (existing ones and new entrants) and the Regulator (ICASA) and focuses mainly on:  Technical Processes and Challenges that must be addressed  Regulatory Process and Challenges that must be addressed  Economic Challenges that must be addressed  Comparison to international ICT Markets and  Recommendations and Conclusions. The dissertation also covers the development of the Local loop unbundling model charter, Local Loop Management website and processes (Annexure A and B) developed (using HTML) used for the management of the unbundling process. Keywords: o Local loop o Caged Co-location / Thesis (M.Ing. (Development and Management Engineering)--North-West University, Potchefstroom Campus, 2009.

The cellular operators (Vodacom, Cell C, MTN and now Virgin Mobile) market has over 39-million mobile phone subscribers and the fixed operator (Telkom) has almost 5 million subscribers [13]. Although the telecommunication sector has been experiencing this significant growth (in terms of numbers), monopolisation of the local loop by Telkom has also resulted in communication prices that are not affordable to the majority of South Africans. The government of South Africa has identified cost of telecommunication services as one of the key initiatives that must be addressed to improve equal levels of access to ICT services in general. Local Loop Unbundling (or LLU for short) has been identified by the South African government as a tool that will minimise control that Telkom has over the copper cable connecting exchanges to customers whilst at the same time driving down the costs of Telecommunication in the country. Although some countries have successfully implemented local loop unbundling, some have not been so successful [3]. This dissertation proposes ICT Systems and processes South Africa needs to have in place to become one of the few success stories. The proposed model was validated against the different models adopted in countries like France, Portugal, United Kingdom and Austria. This dissertation develops a model for implementing local loop unbundling in the South African ICT sector. Local loop unbundling (in short LLU) has been successfully (and unsuccessfully) implemented in a number of countries around the world [3]. The model being proposed recommends best practices to be followed by all stakeholders to ensure successful deployment of local loop unbundling. The research takes a closer look at the South African ICT sector and makes recommendations on processes and systems that are necessary to ensure successful deployment of local loop unbundling in South Africa. The dissertation is written from the view of Telkom (The incumbent Operator), competitors (existing ones and new entrants) and the Regulator (ICASA) and focuses mainly on:  Technical Processes and Challenges that must be addressed  Regulatory Process and Challenges that must be addressed  Economic Challenges that must be addressed  Comparison to international ICT Markets and  Recommendations and Conclusions. The dissertation also covers the development of the Local loop unbundling model charter, Local Loop Management website and processes (Annexure A and B) developed (using HTML) used for the management of the unbundling process. Keywords: o Local loop o Caged Co-location / Thesis (M.Ing. (Development and Management Engineering)--North-West University, Potchefstroom Campus, 2009.

This thesis is focused on the compression algorithm's analysis of MJPEG format and its implementation in FPGA chip. Three additional video bitstream reduction methods have been evaluated for real-time low latency applications of MJPEG format. These methods are noise filtering, inter-frame encoding and lowering video's quality. Based on this analysis, a MJPEG codec has been designed for implementation into FPGA chip XC6SLX45, from Spartan-6 family.

L’augmentation de la taille des réseaux actuels ainsi que de la diversité des applications qui les utilisent font que les architectures de calcul traditionnelles deviennent limitées. En effet, les architectures purement logicielles ne permettent pas de tenir les débits en jeu, tandis que celles purement matérielles n’offrent pas assez de flexibilité pour répondre à la diversité des applications. Ainsi, l’utilisation de solutions de type matériel programmable, en particulier les Field Programmable Gate Arrays (FPGAs), a été envisagée. En effet, ces architectures sont souvent considérées comme un bon compromis entre performances et flexibilité, notamment grâce à la technique de Reconfiguration Dynamique Partielle (RDP), qui permet de modifier le comportement d’une partie du circuit pendant l’exécution. Cependant, cette technique peut présenter des inconvénients lorsqu’elle est utilisée de manière intensive, en particulier au niveau du stockage des fichiers de configuration, appelés bitstreams. Pour palier ce problème, il est possible d’utiliser la relocation de bitstreams, permettant de réduire le nombre de fichiers de configuration. Cependant cette technique est fastidieuse et exige des connaissances pointues dans les FPGAs. Un flot de conception entièrement automatisé a donc été développé dans le but de simplifier son utilisation.Pour permettre une flexibilité sur l’enchaînement des traitements effectués, une architecture de communication flexible supportant des hauts débits est également nécessaire. Ainsi, l’étude de Network-on-Chips dédiés aux circuits reconfigurables et au traitements réseaux à haut débit.Enfin, un cas d’étude a été mené pour valider notre approche. / The increase in both size and diversity of applications regarding modern networks is making traditional computing architectures limited. Indeed, purely software architectures can not sustain typical throughputs, while purely hardware ones severely lack the flexibility needed to adapt to the diversity of applications. Thus, the investigation of programmable hardware, such as Field Programmable Gate Arrays (FPGAs), has been done. These architectures are indeed usually considered as a good tradeoff between performance and flexibility, mainly thanks to the Dynamic Partial Reconfiguration (DPR), which allows to reconfigure a part of the design during run-time.However, this technique can have several drawbacks, especially regarding the storing of the configuration files, called bitstreams. To solve this issue, bitstream relocation can be deployed, which allows to decrease the number of configuration files required. However, this technique is long, error-prone, and requires specific knowledge inFPGAs. A fully automated design flow has been developped to ease the use of this technique. In order to provide flexibility regarding the sequence of treatments to be done on our architecture, a flexible and high-throughput communication structure is required. Thus, a Network-on-Chips study and characterization has been done accordingly to network processing and bitstream relocation properties. Finally, a case study has been developed in order to validate our approach.

Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration interfaces available, the Joint Test Action Group (JTAG) standard for serial communication is the most universally compatible interface due to its use for verifying integrated circuits and testing printed circuit board connectivity. This universality makes it a good interface for tools seeking to access FPGA configuration memory. This thesis introduces a new tool architecture for high-speed, programmable JTAG access to FPGA configuration memory. This tool, called the JTAG Configuration Manager (JCM), is made up of a large C++ software library that runs on an embedded micro-processor coupled with a hardware JTAG controller module implemented in programmable logic. The JCM software library allows for the development of custom JTAG communication of any kind, although this thesis focuses on applications related to FPGA reliability. The JCM hardware controller module allows these software-generated JTAG sequences to be streamed out at very high speeds. Together the software and hardware provide the high-speed and programmability that is important for many JTAG applications.