No description available.

No description available.

The computational power and algorithms needed to create a cognitive radio are quickly becoming available. There are many advantages to having a radio operated by cognitive engine, and so cognitive radios are likely to become very popular in the future. One of the main difficulties associated with the cognitive radio is ensuring the signal transmitted will follow all FCC rules. The work presented in this thesis provides a methodology to guarantee that all signals will be legal and valid. The first part to achieving this is a practical and easy to use software testing program based on the tabu search algorithm that tests the software off-line. The primary purpose of the software testing program is to find most of the errors, specially structural errors, while the radio is not in use so that it does not affect the performance of the system. The software testing program does not provide a complete assurance that no errors exist, so to supplement this deficit, a built-in self-test (BIST) is employed. The BIST is designed with two parts, one that is embedded into the cognitive engine and one that is placed into the radio's API. These two systems ensure that all signals transmitted by the cognitive radio will follow FCC rules while consuming a minimal amount of computational power. The software testing approach based on the tabu search is shown to be a viable method to test software with improved results over previous methods. Also, the software BIST demonstrated its ability to find errors in the signal production and is dem to only require an insignificant amount of computational power. Overall, the methods presented in this paper provide a complete and practical approach to assure the FCC of the legality of all signals in order to obtain a license for the product. / Master of Science

Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear dependencies present in the LFSM generated test-bit sequences adversely affect the resultant fault coverage in two-dimensional scan designs. In this work, we present methods that improve the resultant fault coverage in two-dimensional scan designs through the minimization of linear dependencies. Currently, metric of channel separation and matrix-based metric are used in order to estimate linear dependencies in a CUT. When the underlying sub-circuit (cone) structure of a CUT is available, the matrix-based metric can be used more effectively. Fisrt, we present two methods that use matrix-based metric and minimize the overall linear dependencies in a CUT through explicitly minimizing linear dependencies in the highest number of underlying cones of the CUT. The first method minimizes linear dependencies in a CUT through the selection of an appropriate LFSM structure. On the other hand, the second method synthesizes a phase shifter for a specified LFSM structure such that the overall linear dependencies in a CUT are minimized. However, the underlying structure of a CUT is not always available and in such cases the metric of channel separation can be used more effectively. The metric of channel separation is an empirical measure of linear dependencies and an ad-hoc large channel separation is imposed between the successive scan chains of a two-dimensional scan design in order to minimize the linear dependencies. Present techniques use LFSMs with additional phase shifters (LFSM/PS) as PRPGs in order to obtain desired levels of channel separation. We demonstrate that Generalized LFSRs (GLFSRs) are a better choice as PRPGs compared to LFSM/PS and obtain desired levels of channel separations at a lower hardware cost than the LFSM/PS. Experimental results corroborate the effectiveness of the proposed methods through increased levels of the resultant fault coverage in two-dimensional scan designs.

No description available.

On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals with cost-effective BIST methods and Test Pattern Generation (TPG) schemes in BIST for fault detection and diagnosis of analog circuits. Fault-based testing is used in analog domain due to the applicable test methods/ techniques being general and cost-effective. We propose a novel test method causing the Device Under Test (DUT) to saturate or get out of saturation to detect a fault with simple detection hardware. The proposed test method is best suited for use of existing building blocks in Systems-on-Chip (SoC) for implementation of an on-chip test signal generator and test response analyzer. Test generation for a fault in analog circuit is a compute intensive task. A good test generator produces a highly compact test set with less computational effort without trading the fault coverage. In this context, three new test generation methods viz., MultiDetect, ExpoTan, and MultiDiag for testing analog circuits are presented in this thesis. Testing of analog blocks based on circuit transfer function makes the proposed ATPG methods as general-purpose methods for all kinds of LTI circuits. The principle of MultiDetect method, (i.e., selecting a test signal for which the output amplitude difference between good and faulty circuits is minimum when compared to other test signals in an initial test set), helps in the generation of high quality compacted test set with less fault simulations. The experimental results show that the testing of LTI circuits using MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time. The generated test set with MultiDetect method can effectively detect both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as Built In Self Test (BIST). Test generation for a list of faults and test set compaction are two different phases in an ATPG process. To build an efficient ATPG, these two phases need to be combined with a technique such that the generated test set is highly compact and efficient with less fault simulations. In this context, a novel test set selection technique known as ExpoTan for testing Linear Time Invariant (LTI) circuits is also presented in this thesis. The test generation problem is formulated with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. Identification of a sinusoid that detects more faults results in an optimized test signal set. Fault diagnosis and fault location in analog circuits are of fundamental importance for design validation and prototype characterization in order to improve yield through design modification. In this context, we propose a procedure viz., MultiDiag for generation of a test set for analog fault diagnosis. The analog test generation methods, viz., Max, Rand, and MultiDetect etc., which are based on sensitivity analysis, may fail at times to identify a test signal for locating a fault; because the search for a test signal using these test generation methods is restricted to the limited test signals set. But, the MultiDiag method definitely identifies a test signal, if one exists, for locating a fault.

A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution. Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry. The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.