Capacitive crosstalk noise can affect the delay of a switching signal or induce a glitch on a static signal causing timing violations or chip failure. Crosstalk noise depends on coupling parasitics, driver strength, signal timing characteristics, and signal transition patterns. Layout level crosstalk analysis techniques are generally pessimistic and computationally expensive for large designs due to lack of design flexibility at lower-levels of design hierarchy. The architectural decisions such as type of interconnect architecture, number of storage and execution units, network of communicating units, data bus width, etc., have a major impact on the quality of design attributes such as area, speed, power, and noise. To address all these concerns, we propose a high-level synthesis framework to optimize for worst-case crosstalk patterns on coupled nets, a floorplan driven high-level synthesis framework to minimize coupling capacitance, and an on-chip technique to dynamically detect and eliminate worst-case crosstalk pattern on bus-based macro-cell designs. Due to Miller coupling effect, the switching activity pattern on adjacent nets may increase the effective capacitance seen by a victim net and thereby it may cause a worst-case signal delay on the victim net. However, signal activity pattern on coupled nets are dependent on data correlations which in turn depend on resource sharing. The resource sharing in turn depends on scheduling, allocation, and binding during high-level synthesis flow. Therefore, we propose a Simulated Annealing (SA) based design space exploration of HLS design subspace, bus line re-ordering, and encoding subspaces to optimize for worst-case crosstalk pattern in bus-based macro-cell designs. We demonstrate that the proposed framework will aid layout level techniques in eliminating false positive violations. We also propose an SA based algorithm to explore floorplan and HLS subspaces to optimize coupling capacitances in bus-based macro-cell designs. We have integrated an RTL floorplanner in HLS flow to estimate coupling capacitances between bus lines. Crosstalk analysis using Cadence Celtic shows that the designs generated by the proposed framework results in less number of crosstalk violations compared to designs generated through traditional ASIC design flow. We also propose an on-chip crosstalk detection and elimination technique that dynamically detects and eliminates worst-case crosstalk pattern with minimum area penalty compared to other layout level techniques reported in the literature.

在耐延遲網路(Delay Tolerant Network)中，因為節點具有移動性，因此找不到穩定且持續的點對點資料傳送路徑。常見的路由協定可分為機會路由、基於預測的路由以及調度路由，然而這些路由協定使用在市區環境中，有著些許不足與不適用，因此本論文提出一個適用在市區資料傳送的演算法。 本論文提出之混合階層式路由演算法，是在市區環境中建立一個以公車為基礎的資料傳送架構，包含行人與公車兩種節點。我們建立節點與節點相遇時資料交換傳送規則，例如行人與行人相遇、行人與公車相遇或是公車與公車相遇時各自有不同的資料傳送判斷與限制。 實驗結果也證明所提出之混合階層式演算法，除了可以有效地減少傳送延遲時間並提高訊息傳送成功率，並且在給定節點一定的移動速度與緩衝區大小下，我們的演算法有著最突出的效能。 / In Delay Tolerant Networks (DTNs), there is no guarantee that a stable connected path between source and destination nodes always exists because of high node mobility. The current DTN routing protocols can be summarized into three categories: opportunistic, prediction-based and scheduling protocols. However, these routing protocols have some deficiencies and are not specifically focused on the urban areas which have primarily two hierarchical nodes, namely pedestrian and bus nodes. We proposed a Hybrid Hierarchy Routing Protocol, a bus-based architecture for urban areas. We established the rules of data transmission when one node contacts other nodes. More specifically, Ped-to-Ped, Ped-to-Bus and Bus-to-Bus contacts, have different judgments and restrictions for data forwarding. The simulation results demonstrate that the Hybrid Hierarchy Routing Protocol can effectively reduce the delivery delay and improve the successful delivery rate. And in given certain speed and buffer sizes, our algorithm has the most prominent performance.