Orthogonal Frequency Division Multiplexing (OFDM) plays an important role in the implementation of high data rate communication. In this thesis, the problems of data detection and channel and carrier frequency offset estimation in OFDM systems are studied. <p>Multi-symbol non-coherent data detection is studied which performs data detection by processing multiple symbols without the knowledge of the channel impulse response (CIR). <p>For coherent data detection, the CIR needs to be estimated. Our objective in this thesis is to work on blind channel estimators which can extract the CIR using just one block of received OFDM data. A blind channel estimator for (Single Input Multi Output) SIMO OFDM systems is derived. The conditions under which the estimator is identifiable is studied and solutions to resolve the phase ambiguity of the proposed estimator are given.<p>A channel estimator for superimposed OFDM systems is proposed and its CRB is derived. The idea of simultaneous transmission of pilot and data symbols on each subcarrier, the so called superimposed technique, introduces the efficient use of bandwidth in OFDM context. Pilot symbols can be added to data symbols to enable CIR estimation without sacrificing the data rate. Despite the many advantages of OFDM, it suffers from sensitivity to carrier frequency offset (CFO). CFO destroys the orthogonality between the subcarriers. Thus, it is necessary for the receiver to estimate and compensate for the frequency offset. Several high accuracy estimators are derived. These include CFO estimators, as well as a joint iterative channel/CFO estimator/data detector for superimposed OFDM. The objective is to achieve CFO estimation with using just one OFDM block of received data and without the knowledge of CIR.

A successive interference cancellation (SIC) structure is proposed for multiuser interference cancellation (MUI) due to carrier frequency offsets (CFOs) in the uplink of orthogonal frequency division multiple access (OFDMA) systems. The proposed architecture adopts a circular convolution to suppress the impacts caused by CFOs. This paper demonstrates that, with 2 iterations, the SIC has better performance than that of the parallel interference cancellation (PIC), but system complexity is only 1/2K, where K is the number of users in the uplink of OFDMA system. This study also shows that system complexity can be significantly reduced if proper approximation is made.

This master thesis analyzes the effect of Carrier Frequency Offsets (CFO) on LTEuplink transmission, which is the main cause of ICI (Inter Carrier Interference) andMAI (Multiuser Access Interference). A model of the LTE uplink is required toconduct the study and is implemented in MATLAB, in compliance with 3GPPspecifications. The model can generate uplink signal as generated by the UE, (UserEquipment) and it supports multiple channel bandwidths described by the 3GPP.The channel estimation is done with the help of block type pilots. The model is usedto simulate the experimental conditions. The presence of CFO results in poor systemperformance. Therefore, many algorithms have been proposed for the CFOcancellation such as Successive Interference Cancellation (SIC), Parallel InterferenceCancellation (PIC) and Inverse Interference Matrix Cancellation. As the topic is verybroad, I investigate the performance of Inverse Interference Matrix Cancellationalgorithm. Compared with the other CFO cancellation algorithms this algorithm candirectly estimate the interference components from the inverse pilot matrix, thusthere is no need for CFO estimation. Simulation results show that the algorithm isvery effective in the presence of CFO. The channel estimation technique used is theLeast Square (LS) method and frequency selective channel is used for simulation.Performance graphs are plotted in terms of BER (Bit Error Rate) against differentvalues of SNR (Signal to Noise Ratio).

This thesis investigates the IEEE 802.11b standard that describes radio communication for networks. The standard is carefully explained and the limitations of the standard are presented. To put the system in its context and to study the effects from the frequency translation, surrounding areas such as radio propagation and networks in general are presented. For radio communications the carrier frequency gives the basic properties for the application, long distance communication uses low frequencies and the opposite for short-range communication. The report investigates the possibilities to translate the frequency for an IEEE 802.11b system to move the limits of IEEE 802.11b Three alternative solutions are compared. A final solution evolves from one of them. The resulting solution is based on existing hardware and is ready for testing. One major conclusion is that 802.11b is a well developed standard where the development of the hardware is focussed on the physical size. This miniaturization makes alteration more complex. Finally other interesting wireless techniques that could give the desired properties and other possible further work are presented.

Wireless communication systems utilize the wireless medium to perform over-the-air (OTA) data transfer. There are many factors that can impact the quality of wireless communications, such as medium imperfection, interfering environment, mismatch of transceivers, etc. To mitigate these problems and improve the quality of service (QoS), this research study is conducted on three important topics including synchronization techniques, impairment estimation theory and techniques, and interference alignment techniques. In this thesis, it firstly present a dual link algorithm to align and manage the interference of multiple-input and multiple-output (MIMO) networks. A field-programmable gate array (FPGA) prototype is designed for software defined radio (SDR) platforms. As one of the key components, a hardware efficient architecture is proposed for the implementation of singular value decomposition (SVD). Secondly, it proposes a maximum-likelihood (ML) based synchronization approach for carrier frequency synchronization for MIMO systems. The algorithm is also implemented on FPGA for real-time performance evaluation. Finally, as an exemplary study of machine learning techniques for wireless communications, a neural network (NN) based estimator is proposed to perform coarse frequency offset estimations for MIMO systems. The proposed NN based estimator can accommodate various channel models and the results show promising performance in terms of accuracy and estimation range. In summary, this thesis provides a comprehensive study on interference alignment, carrier synchronization, and impairment estimation using different approaches. Efficient hardware implementations for the key algorithms are also presented.

Wireless communication systems utilize the wireless medium to perform over-the-air (OTA) data transfer. There are many factors that can impact the quality of wireless communications, such as medium imperfection, interfering environment, mismatch of transceivers, etc. To mitigate these problems and improve the quality of service (QoS), this research study is conducted on three important topics including synchronization techniques, impairment estimation theory and techniques, and interference alignment techniques. In this thesis, it firstly present a dual link algorithm to align and manage the interference of multiple-input and multiple-output (MIMO) networks. A field-programmable gate array (FPGA) prototype is designed for software defined radio (SDR) platforms. As one of the key components, a hardware efficient architecture is proposed for the implementation of singular value decomposition (SVD). Secondly, it proposes a maximum-likelihood (ML) based synchronization approach for carrier frequency synchronization for MIMO systems. The algorithm is also implemented on FPGA for real-time performance evaluation. Finally, as an exemplary study of machine learning techniques for wireless communications, a neural network (NN) based estimator is proposed to perform coarse frequency offset estimations for MIMO systems. The proposed NN based estimator can accommodate various channel models and the results show promising performance in terms of accuracy and estimation range. In summary, this thesis provides a comprehensive study on interference alignment, carrier synchronization, and impairment estimation using different approaches. Efficient hardware implementations for the key algorithms are also presented.

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field.<p> A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market.<p> Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. <p> The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. <p> A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation.<p> Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. <p> A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field.<p> A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market.<p> Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. <p> The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. <p> A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation.<p> Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. <p> A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection.