Short Word-Length refers to single-bit, two-bit or ternary processing systems. SWL systems use Sigma-Delta Modulation (SDM) technique to express an analogue or multi-bit input signal in terms of a high frequency single-bit stream. In Sigma-Delta Modulation, the input signal is coarsely quantized into a single-bit representation by sampling it at a much higher rate than twice the maximum input frequency viz. the Nyquist rate. This single-bit representation is almost exclusively filtered to remove conversion quantization noise and sample decimated to the Nyquist frequency in preparation for traditional signal processing. SWL algorithms have a huge potential in a variety of applications as they offer many advantages as compared to multi-bit approaches. Features of SWL include efficient hardware implementation, increased flexibility and massive cost savings. Field Programmable Gate Arrays (FPGAs) are SRAM/FLASH based integrated circuits that can be programmed and re-programmed by the end user. FPGAs are made up of arrays of logic gates, routing channels and I/O blocks. State-of-the-art FPGAs include features such as Advanced Clock Management, Dedicated Multipliers, DSP Slices, High Speed I/O and Embedded Microprocessors. A System-on-Programmable-Chip (SoPC) design approach uses some or all the aforementioned resources to create a complete processing system on the device itself, ensuring maximum silicon area utilization and higher speed by eliminating inter-chip communication overheads. This dissertation focuses on the application of SWL processing systems in audio Class-D Amplifiers and aims to prove the claims of efficient hardware implementation and higher speeds of operation. The analog Class-D Amplifier is analyzed and an SWL equivalent of the system is derived by replacing the analogue components with DSP functions wherever possible. The SWL Class-D Amplifier is implemented on an FPGA, the standard emulation platform, using VHSIC Hardware Description Languages (VHDL). The approach is taken a step forward by adding re-configurability and media selectivity and proposing SDM adaptivity to improve performance.

<p>Class D amplifiers are becoming increasingly popular in audio devices. The strongest reason is the high efficiency which makes it advantageous for portable battery-driven products.</p><p>Infineon Technologies is developing products in this area, and has recently filed a patent application regarding an implementation of a part of the class D amplifier. The aim of this Master’s thesis is to evaluate a digital open-loop implementation of a class D amplifier, using the pending patent solution, and discuss the differences from an analog closed-loop implementation.</p><p>The focus has been on generating a high resolution PWM signal with a relatively low clock frequency. To achieve this, a hybrid of a counter and a self-calibrating tapped delay-line are used as a pulse generator. A model of the pulse generator was developed which made it possible to study how sampling frequency and different types of quantization affected quality parameters such as THD and SNR. With the results from the model two systems were implemented and simulated in HDL and as circuit schematics.</p><p>The proposed digital open-loop class D amplifier was found to be useful in voice-band applications and for music. Since the open-loop structure suffers from poor rejection of power supply ripple, either error correction or a regulated power supply is needed. If much effort is put on the different parts of the amplifier the result can be really good but, depending on other constraints on the system, it may be simpler and less time consuming to use the analog circuit with feedback to achieve hi-fi quality.</p><p>In summary, the combination of a counter and a self-calibrating tapped delay-line as a pulse generator is very useful in high resolution low-power systems. To avoid errors the delay-line and calibration can be made very accurate but with the expense of higher power consumption and area. However, the technique benefits from the small and fast logic devices available in deep sub-micron process technologies, which may finally lead to an advantage in power consumption and cost over the closed-loop analog solution.</p>

Class D amplifiers are becoming increasingly popular in audio devices. The strongest reason is the high efficiency which makes it advantageous for portable battery-driven products. Infineon Technologies is developing products in this area, and has recently filed a patent application regarding an implementation of a part of the class D amplifier. The aim of this Master’s thesis is to evaluate a digital open-loop implementation of a class D amplifier, using the pending patent solution, and discuss the differences from an analog closed-loop implementation. The focus has been on generating a high resolution PWM signal with a relatively low clock frequency. To achieve this, a hybrid of a counter and a self-calibrating tapped delay-line are used as a pulse generator. A model of the pulse generator was developed which made it possible to study how sampling frequency and different types of quantization affected quality parameters such as THD and SNR. With the results from the model two systems were implemented and simulated in HDL and as circuit schematics. The proposed digital open-loop class D amplifier was found to be useful in voice-band applications and for music. Since the open-loop structure suffers from poor rejection of power supply ripple, either error correction or a regulated power supply is needed. If much effort is put on the different parts of the amplifier the result can be really good but, depending on other constraints on the system, it may be simpler and less time consuming to use the analog circuit with feedback to achieve hi-fi quality. In summary, the combination of a counter and a self-calibrating tapped delay-line as a pulse generator is very useful in high resolution low-power systems. To avoid errors the delay-line and calibration can be made very accurate but with the expense of higher power consumption and area. However, the technique benefits from the small and fast logic devices available in deep sub-micron process technologies, which may finally lead to an advantage in power consumption and cost over the closed-loop analog solution.

This thesis presents a novel three-level modulation technique for a Class-D audio amplifier, attempting to improve the poor performance of the conventional two-level modulation scheme at low input levels. The main drawback of the conventional two-level PWM (pulse-width modulation) and SDM (sigma-delta modulation) Class-D amplifier is that, with a zero input or small input, the excessively fast switching action at the output causes unwanted switching loss and switching noise, resulting in unnecessary energy waste and SNDR degradation. The presented three-level modulation circuit mainly consists of a linear feedback compensator, two comparators, and a switching logic circuit. The simulation and experimental results shows that the proposed three-level modulation s cheme outperforms the two-level sigma-delta modulation scheme in both efficiency and performance.

The systems which contain coarsely quantized signals are commonly found in applications where the actuators and/or sensors can only output a finite number of levels. This thesis focuses on the problem of synthesizing a finite-level control force for a certain control task, first presenting a systematic design method based on the theory of sliding modes and then applying it to the designs of the class-D audio amplifier and synchronous buck converter. At the first part, a novel three-level modulation technique for a class-D audio amplifier is designed by the sliding mode control theory. The simulated and experimental results conform to the excellent performance of this three-level modulation scheme. In particular, the proposed modulation scheme improves the poor efficiency of a conventional two-level class-D audio amplifier when the audio input signal is small, also excludes the output LC filter. The experiment shows that the designed three-level class-D amplifier achieves a minimum total harmonic distortion plus noise of 0.039% and an efficiency of 85.18%. At the second part, the controller of a synchronous buck converter is designed. The proposed self-oscillating controller stabilizes the buck converter in sliding mode, without the need of a triangular wave generator like the conventional PWM method. A 12V/1.5V synchronous buck converter with proposed control is built in the laboratory. The experiment shows 0.66% of the static output ripple and 3% of the load regulation error in response to the 15A step change of the load current at a slew rate of 50A/£gs.

This thesis focuses on the design and implementation of a three-level Class D audio amplifier by applying recently developed sliding-mode quantized control. The designed controller, which consists of the analog filters and logic circuit, switches an H-bridge Class-D amplifier with a lowpass LC filter and operates it in the sliding mode, in order to achieve desired stability and high fidelity in the audio band. The experimental result shows that the lowest THD+N (total harmonic distortion plus noise) can be as low as 0.02% at 1 kHz. The performance is better than most of the available commercial products.

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text

Η ψηφιακή τεχνολογία έχει διεισδύσει πλήρως στην περιοχή της Ακουστικής και της Τεχνολογίας Ήχου, όπως επίσης και σε όλους σχεδόν τους κλάδους της σύγχρονης επιστήμης και της τεχνολογίας. Στον τομέα των ηλεκτρονικών για ηχητικές εφαρμογές, ιδιαίτερα καθοριστικό ρόλο κατέχουν οι ενι- σχυτές. Σκοπός της εργασίας αυτής, είναι να παρουσιάσει το λειτουργικό μοντέλο ενός ψηφιακού ενι- σχυτή Class-D για ηχητικά σήματα, το οποίο προσομοιώθηκε και λειτούργησε σε περιβάλλον Matlab & Simulink. Στο τέλος παρουσιάζονται τα αποτελέσματα χρήσιμων μετρήσεων για σημαντικούς δεί- κτες της ηλεκτροακουστικής όπως η Απόκριση Συχνότητας, Total Harmonic Distortion(THD), Total Harmonic Distortion plus Noise (THD+N) ως προς τη συχνότητα και ως προς την ισχύ, από όπου βγαίνουν συμπεράσματα σχετικά με την ποιότητα και την απόδοση της συγκεκριμένης τεχνολογίας υλοποίησης. / DigitalTechnology has been fully into Acousctics and Audio Technology,as in virtually all branches of modern science and technology.In audio electronics applications, amplifiers have a significant role. The purpose of this thesis is to present the functional model of a digital Class-D amplifier for audio signals, which has been simulated and run in Matlab & Simulink environment. Finally the results of measurements relating to some important electroacoustics indexes like Frequency Response, Total Harmonic Distortion (THD), Total Harmonic Distortion plus Noise (THD+N), relative to the audio signal’s frequency and power, are presented and lead to some conclusions concerning the quality and efficiency of this implementation technology.

Αντικείμενο αυτής της διπλωματικής υπήρξε η μελέτη μιας νέας μεθόδου ενίσχυσης ακουστικών συχνοτήτων, που μπορεί να αναπαράγει τον ήχο με την υψηλή ποιότητα των ενισχυτών τάξης Α και ταυτόχρονα με υψηλή απόδοση ισχύος, που χαρακτηρίζει τους ενισχυτές τάξης D. / This Diploma Thesis studies a new method of audio amplifying that can reproduce sound with both high fidelity as found in a class A amplifier and high efficiency which is characteristic of class D amplifier.

The goal of this master thesis was to study the theory and to realize an induction loop for railway rolling vehicles, to design and manufacture a functioning prototype of electronic amplifier, which carries out all the requirements. This thesis includes detailed information about the induction loop system, its position and performance, following with the design of the amplifier, execution of the design and with the conclusion of measured parameters for the accomplishment of the required parameters.