This diploma thesis deals with digital audio amplifier with universal inputs and its design. The first part describes modulation and audio formats for audio electronics. The thesis contain design of a block diagram of the digital audio amplifier and describes the requirements for functional blocks. As a basic device for audio signal processing was choosen integrated circuit STA326. The thesis continue with circuits design for each blocks with a description of their principles. The next section describes the construction and firmware for microcontroller. The last part of this diploma thesis is targeted on the presentation of the measured parameters of the amplifier. The conclusion summarizes the results that have been achieved and advantages and disadvantages of the digital audio amplifier prototype.

The thesis deals with the design and practical realization of class D audio power amplifier with microprocessor controlling. The first part describes the integrated circuits used in a preamplifier and his complete design with a description of the control program for ATmega128 microcontroller. The following part describes an integrated power amplifier TAS5613 and his circuits. The next section describes a switching power supply design using integrated circuit TOP261EN. The last section describes measurements of parameters of individual parts of the amplifier.

Usage of class D audio amplifiers has become increasingly widespread in recent years, mainly due to their high efficiency, which can reach almost 100 %. Class D amplifiers can also be compact, making them suitable for mobile applications. In contrast, the most efficient conventional amplifiers such as class B can reach a maximum efficiency of 78.5 %. The high efficiency of class D amplifiers can be attributed to the switching stage, which in the case of a half-bridge design consists of two amplifying MOSFETs. These MOSFETs are never on at the same time, which minimizes the quiescent current and thereby the power losses. The goal of this project was to design, simulate and construct a half-bridge class D audio amplifier. A working amplifier with 80 % efficiency was built, with power losses occuring mainly in the voltage regulators. Simulations of the amplifier corresponded well with the constructed amplifier apart from issues originating from the aforementioned voltage regulation as well as the triangle wave generator. The goal of the project was achieved and the finished amplifier possessed good sound quality and little unwanted noise. To further improve on the design, better voltage regulation, a full-bridge configuration and a feedback loop could be utilized.

An investigation into performance improvements to the modulator stage of a class-D amplifier is conducted in this thesis. Two of the standard topologies, namely class-D open-loop pulse-width modulation (PWM), and the improved self-oscillating feedback system are benchmarked against a topology which includes both a hysteretic comparator in a feedback loop and triangle wave injection. Circuit performance is analyzed by comparing how the triangle injection circuit handles known issues with open-loop and self-oscillating circuits. Using this analysis, it is shown that the triangle injection topology offers an improved power supply rejection ratio relative to open-loop PWM and reduces distortion generated by frequency modulation characteristic of the self-oscillating topology.

This thesis was written at Airbus DS GmbH in Friedrichshafen, Germany, as part of a project which aims to develop a new generation of class-D power amplification circuits for sinusoidal commutating motors controlling the movement of different mechanisms in satellites. Currently used topologies have disadvantages such as high power loss, analog controlling and high degree of signal distortion. This work first simulates available topologies which were previously developed by the company in order to compare them and build a trade-off list so the most suitable circuit is selected. Then, by further simulating and analysis several improvements to the circuit are suggested and a final schematic is developed including an analogue-to-digital converter and a total of three phases to power a motor. After a demonstrator circuit was designed and built, it was tested by using an external real time target machine to generate the corresponding PWM signals in correspondence to a controlling signal generated via Simulink. The final product of this thesis confirmed the simulation results such as an improved signal quality at higher frequencies in comparison to an available measurement from a previous generation circuit. The flexibility of the topology as well as the possibility of implementing a digital control was also confirmed during this phase of the project. Upon further work, the dimensioning of the output low pass filter should be improved and a digital PID controller should be implemented in the controlling FPGA. / <p>This version of the Master Thesis deviates from the formal original submitted for examination in order not to disclose confidential information of Airbus DS GmbH. All positions in the document, where additional information was removed are properly identified. This document can be published according to the general rules of the Julius-Maximilians-Universität Würzburg and the Lulea University of Technology.</p>

Modern wireless communication techniques employed in the Wi-Fi® protocol, such as orthogonal frequency-division multiplexing exhibit analogue signals with high peak-to-average power ratio. Therefore, power amplifiers for Wi-Fi suffer from low efficiency when operating in back-off mode, away from their maximum efficiency at peak power. In recent years, digital power amplifiers have been developed to replace their analogue equivalent, taking advantage of easier scaling and circumventing transition frequency issues. Since the digital power amplifier technology for Wi-Fi application is recent, it has not yet replaced robust analogue amplifiers in industrial context. This work proposes to investigate the feasibility and complexity to replace an analogue amplifier with its digital counterpart, with at least the same specification. Among several possible architectures, the reverse class D is chosen for its apparent simplicity. It achieves low power loss into transistors parasitics by operating in square-current mode instead of voltage mode, hence displaying a current-based RF-DAC behaviour. After elaborating the core design with simple efficiency enhancement techniques specific to reverse class D, the layout of the circuitry has been designed. Post-layout simulations have shown the reverse class D digital amplifier designed in CMOS 22nm achieves the required specification of 18dBm average output power with -28dB error vector magnitude in the 2.4GHz range. This basic architecture achieves 19% average drain efficiency, a small improvement over its analogue equivalent currently in use. / Moderna trådlösa kommunikationstekniker som används i Wi-Fi®-protokollet, till exempel ortogonal frekvensdelningsmultiplexering, uppvisar analoga signaler med hög variation i amplitud. Därför har effektförstärkare för Wi-Fi låg verkningsgrad eftersom de arbetar i back-off-läge, långt ifrån sin maximala verkningsgrad vid hög uteffekt. Under de senaste åren har digitala effektförstärkare utvecklats för att byta ut deras analoga motsvarigheter. Eftersom digitala effektförstärkare för Wi-Fi är nya, har de ännu inte ersatt robusta analoga förstärkare i industriella sammanhang. I detta arbete föreslås en undersökning av genomförbarheten och komplexiteten i att ersätta en analog förstärkare med dess digitala motsvarighet, med åtminstone samma specifikation. Bland flera möjliga arkitekturer har den strömbaserade klass D valts på grund av sin enkelhet. Den uppnår låg effektförlust i transistorparasiter genom att arbeta i strömsläge istället för i spänningsläge, och fungerar som en strömbaserade RF-DAC. Efter att ha utarbetat kärnkonstruktionen med enkla tekniker för effektivitetsförbättring som är specifika för strömbaserade klass D har kretsens layout utformats. Simuleringar efter layouten har visat att den digitala förstärkaren i strömbaserade klass D som konstruerats i CMOS 22nm uppnår den nödvändiga specifikationen på 18 dBm genomsnittlig uteffekt med -28 dB felvektorstorlek vid 2,4 GHz. Denna arkitektur uppnår en genomsnittlig verkningsgrad på 19%, vilket är en liten förbättring jämfört med den analoga motsvarighet som för nuvarande används.

Let Ω be the Fraïssé limit of a class of relational structures. We seek to answer the following semigroup theoretic question about Ω. What are the group H-classes, i.e. the maximal subgroups, of End(Ω)? Fraïssé limits for which we answer this question include the random graph R, the random directed graph D, the random tournament T, the random bipartite graph B, Henson's graphs G[subscript n] (for n greater or equal to 3) and the total order Q. The maximal subgroups of End(Ω) are closely connected to the automorphism groups of the relational structures induced by the images of idempotents from End(Ω). It has been shown that the relational structure induced by the image of an idempotent from End(Ω) is algebraically closed. Accordingly, we investigate which groups can be realised as the automorphism group of an algebraically closed relational structure in order to determine the maximal subgroups of End(Ω) in each case. In particular, we show that if Γ is a countable graph and Ω = R,D,B, then there exist 2[superscript aleph-naught] maximal subgroups of End(Ω) which are isomorphic to Aut(Γ). Additionally, we provide a complete description of the subsets of Q which are the image of an idempotent from End(Q). We call these subsets retracts of Q and show that if Ω is a total order and f is an embedding of Ω into Q such that im f is a retract of Q, then there exist 2[superscript aleph-naught] maximal subgroups of End(Q) isomorphic to Aut(Ω). We also show that any countable maximal subgroup of End(Q) must be isomorphic to Zⁿ for some natural number n. As a consequence of the methods developed, we are also able to show that when Ω = R,D,B,Q there exist 2[superscript aleph-naught] regular D-classes of End(Ω) and when Ω = R,D,B there exist 2[superscript aleph-naught] J-classes of End(Ω). Additionally we show that if Ω = R,D then all regular D-classes contain 2[superscript aleph-naught] group H-classes. On the other hand, we show that when Ω = B,Q there exist regular D-classes which contain countably many group H-classes.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.