In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in determining circuit performance including timing, power consumption, cost, power supply noise and tolerance to process variations. It is required that a clock layout algorithm can achieve any prescribed skews with the minimum wire length and acceptable slew rate. Traditional zero-skew clock routing methods are not adequate to address this demand, since they tend to yield excessive wire length for prescribed skew targets. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area, which results in lesser cost, power consumption and vulnerability to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper slew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the algorithm can reduce the total wire and buffer capacitance by 60% over an extension of the existing zero-skew routing method.

In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in determining circuit performance including timing, power consumption, cost, power supply noise and tolerance to process variations. It is required that a clock layout algorithm can achieve any prescribed skews with the minimum wire length and acceptable slew rate. Traditional zero-skew clock routing methods are not adequate to address this demand, since they tend to yield excessive wire length for prescribed skew targets. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area, which results in lesser cost, power consumption and vulnerability to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper slew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the algorithm can reduce the total wire and buffer capacitance by 60% over an extension of the existing zero-skew routing method.

A hardware design methodology or platform is complete if it has the capabilities to successfully implement clock tree, predict the power consumption for cases like best and worst Parasitic Interconnect Corners (RC Corners), supply power to every standard cell, etc.This thesis has tried to solve the three unsolved engineering problems in SiLago design. First, power characterization of the flat design which was designed using the SiLago methodology. Second, designing a hierarchical clock tree and harden it inside the SiLago logic. Third, dimensioning hierarchical power grids. Out of these, clock tree illustrates some interesting characteristics as it is programmable and predictable.The tools used for digital designing are Cadence Innovus, Synopsys Design Vision, and Mentor Graphics Questasim. These are very sophisticated tools and widely accepted in industries as well as in academia.The work done in this thesis has enabled SiLago platform one step forward toward its fruition. / En hårdvarudesign metodologi eller plattform är komplett om den har kapabiliteten till att lyckas genomföra klockträdet, förutsäga strömförbrukningen för bästa och värsta fall av Parasitic Interconnect Corners (RC Corners), tillföra kraft till varje standardcell, etc. Denna avhandling har försökt lösa de tre olösta tekniska problemen i SiLago-designen. Det första är strömkvalificering av designen som designades med hjälp av SiLago metoden. Det andra problemet är att designa ett hierarkiskt klockträd och härda det inuti SiLago logik. Det tredje problemet är att dimensionera hierarkiska strömnät. Ur dessa illustrerar klockträdet några intressanta egenskaper eftersom det är programmerbart och förutsägbart. De verktyg som används för digital design är Cadence Innovus, Synopsys Design Visionoch Mentor Graphics Questasim. Dessa verktyg är mycket sofistikerade och allmänt accepterade i industrier såväl som i akademin. Arbetet i denna avhandling har gjort det möjligt för SiLago-plattformen att ta ett steg mot att realiseras.

Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance lost due to process variations. Then we study the impact of positioning of tunable buffers in the clock tree. In course of our study it was observed that the greatest benefit from tunable buffer placement can be derived, when the clock tree is synthesized with future tuning considerations. Accordingly, we present a clock tree synthesis procedure which offers very good mitigation against process variation, as borne out by the results. The results show that without any design intervention, an average improvement of 9% is achieved by our tuning system. However, when the clock tree is synthesized based on static timing information with tuning buffer placement considerations, much larger performance improvement is possible. In one example, performance improved by as much as 18%.