The thesis is composed of tow topics: a high performance current-balancing instrumentation amplifier (IA) for ECG (Electrocardiogram) monitoring systems and an IA with CMRR (Common-Mode Rejection Ratio) self-calibration. In the first topic, a high common mode rejection ratio (CMRR) and a low input referred noise instrumentation amplifier (IA) is presented for ECG applications. A high pass filter (HPF) with a small-Gm OTA using a current division technique is employed to attain small transconductance, which needs only a small capacitor in the HPF such that the integration on silicon is highly feasible. The proposed design is carried out by TSMC standard 0.18 £gm CMOS technology. CMRR is found to be 127 dB and the voltage gain is 45 dB according to the simulation results. The second topic discloses an instrumentation amplifier with CMRR self-calibration capability. The propose design is also carried out by TSMC standard 0.18 £gm CMOS technology. To achieve a CMRR of more than 80 dB, a calibration resistance string and a detection circuit have been utilized. The DC gain of the proposed design is 60 dB and the frequency bandwidth is bound in 10 KHz, which is adaptable for biomedical signal acquisition applications.

Recently, it became possible to detect single motor units (MUs) noninvasively via the use of spatial filtering electrode arrays. With these arrays, weighted combinations of monopolar electrode signals recorded from the skin surface provide spatial selectivity of the underlying electrical activity. Common spatial filters include the bipolar electrode, the longitude double differentiating (LDD) filter and the normal double differentiating (NDD) filter. In general, the spatial filtering is implemented in hardware and the performance of the spatial filtering apparatus is measured by its common mode rejection ratio (CMRR). High precision hardware differential amplifiers are used to perform the channel weighting in order to achieve high CMRR. But, this hardware is expensive and all channel weightings must be predetermined. Hence, only a few spatially filtered channels are typically derived. In this project, a distinct software equalization filter was cascaded with each of the hardware monopolar signal conditioning circuits to achieve accurate weighting and high CMRR. The simplest technique we explored was to design an equalization filter by dividing the frequency response of a“reference" (or“ideal") channel by the measured frequency response of the channel being equalized, producing the desired equalization filter in the frequency domain (conventional technique). Simulation and experimental results showed that the conventional technique is very sensitive to broadband background noise, producing poor CMRR. Thus, a technique for signal denoising that is based on signal mixing was pursued and evaluated both in simulation and laboratory experiments. The purpose of the mixing technique is to eliminate the noise as much as possible prior to equalization filter design. The simulation results show that without software equalization, CMRR is only around 30 dB; with conventional technique CMRR is around 50~60 dB. By using mixing technique, CMRR can be around 70~80 dB.

There are two major design problems for upper seam longwall gateroads operating in a multi-seam environment. The first is to determine the location, magnitude and duration of stress transferred from lower seam mines; and the second is to predict the effect of stress transferred from lower seam mines on opening stability. To solve these problems for both longwall and room-and-pillar mines, case study data were collected and analyzed to develop empirical models predicting upper seam damage created by mining activities in the lower seam. Analysis showed vertical movement in the upper seam and roof CMRR (Coal Mine Roof Rating) to be the controlling factors in damage prediction and, therefore, gateroad planning and design. The relationship between the predicted damage rating and the gateroad stability was established and quantified. To simplify the application of design procedures developed for longwall gateroad systems, the criteria were incorporated in a Windows-based, multi-interface software , UGLY (Upperseam Gateroad Longwall Stability). The programming language was Visual Basic, and the program's design capabilities were validated and demonstrated using case study data. / Master of Science

<p>This master's thesis addresses two main problems. The first is how to suppress a common mode voltage that appears for current shunts, and the second how to let a voltage divider work under an unloaded condition to prevent loading errors and thereby a decreased measurement accuracy. Both these problems occurs during calibration of power meters, and verification of current shunts and voltage dividers. To the first problem three alternative solutions are presented; prototype a proposed instrumentation amplifier circuit, evaluate the commercial available instrumentation amplifier Analog Devices AD8130 or let the voltage measuring device suppress the common mode voltage. It is up to the researchers at SP to choose a solution. To address the second problem, a prototype buffer amplifier is built and verified. Measurements of the buffer amplifier show that it performs very well. At 100 kHz, the amplitude error is less than 20 μV/V, the phase error is less than 20 μrad, and the input R_p is over 10 MΩ. This is performance in line with the required to make accurate measurements possible at 100 kHz and over that.</p>

This master's thesis addresses two main problems. The first is how to suppress a common mode voltage that appears for current shunts, and the second how to let a voltage divider work under an unloaded condition to prevent loading errors and thereby a decreased measurement accuracy. Both these problems occurs during calibration of power meters, and verification of current shunts and voltage dividers. To the first problem three alternative solutions are presented; prototype a proposed instrumentation amplifier circuit, evaluate the commercial available instrumentation amplifier Analog Devices AD8130 or let the voltage measuring device suppress the common mode voltage. It is up to the researchers at SP to choose a solution. To address the second problem, a prototype buffer amplifier is built and verified. Measurements of the buffer amplifier show that it performs very well. At 100 kHz, the amplitude error is less than 20 μV/V, the phase error is less than 20 μrad, and the input Rp is over 10 MΩ. This is performance in line with the required to make accurate measurements possible at 100 kHz and over that.

This thesis describes the design guidelines from two medical teams, electrocardiogram and pulse oximetry using embedded logic circuitry such as FPGA and microcontrollers, digital filters used to filter the signals obtained from analog converters to digital, graphic obtaining the data is displayed in a graphic display GLCD, and has an interface to send data to a PC through a port USB 2 at full speed. The digital filters used are FIR filters, these filters are chosen to be linear and time invariant, developed with 40 coefficients FIR filters, these filters were implemented in the FPGA, use a FPGA that has implemented only 20 multipliers For the implementation we used the VHDL language and algorithmic state machines in order to control the 20 boxes and get the 40 products. Filtered data in the stage of the FPGA, are taken to a microcontroller that is responsible for managing the data, can lead to a graphic display GLCD, and so we can see the signal and obtained values or you can send the data to a PC right through USB port and software right through it can see the graphics on the PC.