Bearing currents are not all the same. Under certain circumstances and special use cases classic bearing insulations are not sufficient anymore to prevent bearing currents due to the operation of frequency converters. Additional corrective measures have to be implemented to reduce the source of bearing currents the common mode current. The usage of nanocrystalline tape wound cores shows high effectiveness. As part of a big field study with more than 50 large drive trains in the primary industry, the damaging mechanics of bearing currents are examined under real conditions. Of exceptional high interest is the influence of disturbances which can hardly be simulated in the laboratory. Additional to the shielded motor cable parallel installed functional potential equalization cables applied multiple times have almost no effect in regard to reducing the bearing current. With an optimal installed functional potential equalization system more than 95 percent of the common mode current can flow back through the motor cable shield to the converter. The disturbance impact in the field can influence the voltage over the bearing that breakthroughs are favored but also reduced.

Recently, matrix converter has received considerable interest as a viable alternative to the conventional back-to-back PWM (Pulse Width Modulation) converter in the ac/ac conversion. This direct ac/ac converter provides some attractive characteristics such as: inherent four-quadrant operation; absence of bulky dc-link electrolytic capacitors; clean input power characteristics and increased power density. However, industrial application of the converter is still limited because of some practical issues such as common mode voltage effects, high susceptibility to input power disturbances and low voltage transfer ratio. This dissertation proposes several new matrix converter topologies together with control strategies to provide a solution about the above issues. In this dissertation, a new modulation method which reduces the common mode voltage at the matrix converter is first proposed. The new method utilizes the proper zero vector selection and placement within a sampling period and results in the reduction of the common mode voltage, square rms of ripple components of input current and switching losses. Due to the absence of a dc-link, matrix converter powered ac drivers suffer from input voltage disturbances. This dissertation proposes a new ride-through approach to improve robustness for input voltage disturbances. The conventional matrix converter is modified with the addition of ride-through module and the add-on module provides ride-through capability for matrix converter fed adjustable speed drivers. In order to increase the inherent low voltage transfer ratio of the matrix converter, a new three-phase high-frequency link matrix converter is proposed, where a dual bridge matrix converter is modified by adding a high-frequency transformer into dc-link. The new converter provides flexible voltage transfer ratio and galvanic isolation between input and output ac sources. Finally, the matrix converter concept is extended to dc/ac conversion from ac/ac conversion. The new dc/ac direct converter consists of soft switching full bridge dc/dc converter and three phase voltage source inverter without dc link capacitors. Both converters are synchronized for zero current/voltage switching and result in higher efficiency and lower EMI (Electro Magnetic Interference) throughout the whole load range. Analysis, design example and experimental results are detailed for each proposed topology.

In this thesis, we use the no-capacitor feed-forward (NCFF) compensation scheme which employs a feed-forward path to obtain high gain, high frequency. We use CMFB circuit to adjust the common-mode output voltages and the bias circuit. The CMFB circuit makes the output accurately to the reference voltage. The circuit was designed and fabricated TSMC 0.35 £gm CMOS process. The dc gain is around 90dB and the cut-off frequency is 1GHz. The supply voltage is ¡Ó1.25V. The output voltage is smaller than 10mV.

Este trabalho apresenta estudos voltados ao teste de Amplificadores Diferenciais. No primeiro momento, por meio de simulações SPICE, falhas catastróficas são injetadas em dois Amplificadores Diferenciais, projetados para uma tecnologia CMOS de 0,5m com configurações complementares, a fim de comprovar a ocorrência de variações nas tensões DC dos nós do circuito sob teste à medida que há injeções de falhas no mesmo. Também se faz análises preliminares dos resultados para verificar a possibilidade de diagnosticar as falhas através de assinaturas compostas pela digitalização (em um bit) dos valores DC dos nós do circuito sob teste. Posteriormente, é desenvolvida uma metodologia de teste simples e com baixo custo, aplicável a Amplificadores Totalmente Diferenciais. Considerando a necessidade do Circuito de Realimentação de Modo Comum para manter o controle do modo comum das saídas, é proposta a reutilização deste circuito como verificador, possibilitando a observação de falhas ocorridas tanto no Amplificador quanto no próprio bloco de CMFB. Falhas catastróficas e paramétricas são injetadas, por simulação, em dois amplificadores totalmente diferenciais, um projetado em 180nm e outro em 130nm. Testes DC e transientes são realizados e a cobertura de falhas é avaliada. Os resultados das simulações apontam boa cobertura de falhas, enquanto apenas os sinais de realimentação de modo comum precisam ser monitorados. Dessa forma é proposta uma estratégia de teste que apresenta um baixo custo e uma baixa sobrecarga de área do circuito. / This work presents a study related to the testing of Differential Amplifiers. Firstly, by means of SPICE simulations, catastrophic faults are injected in two complementary Differential Amplifiers, designed considering a 0,5μm CMOS technology, in order to prove the concept of testing the circuit by checking the occurrence of variations in the DC voltage of the circuit internal nodes due to the injected faults. The possibility of diagnosing faults using a digitized representation of the DC values of the observed nodes of the circuit was also investigated. Then, a simple and cost-effective test methodology for Fully Differential Amplifiers (FDA) is proposed. Considering the need of the common mode feedback circuit to maintain the control of the common mode output voltage, it is proposed to re-use this circuit as a checker, allowing the observation of faults in both the amplifier itself and the CMFB block. Catastrophic and parametric faults are injected in two FDAs, designed in 180nm and 130nm technology respectively. DC and transient tests are performed and the fault coverage is evaluated. The simulation results indicate high fault coverage, while only the signals from the common mode feedback need to be monitored. This way a low cost and low overhead test methodology is proposed.

Este trabalho apresenta estudos voltados ao teste de Amplificadores Diferenciais. No primeiro momento, por meio de simulações SPICE, falhas catastróficas são injetadas em dois Amplificadores Diferenciais, projetados para uma tecnologia CMOS de 0,5m com configurações complementares, a fim de comprovar a ocorrência de variações nas tensões DC dos nós do circuito sob teste à medida que há injeções de falhas no mesmo. Também se faz análises preliminares dos resultados para verificar a possibilidade de diagnosticar as falhas através de assinaturas compostas pela digitalização (em um bit) dos valores DC dos nós do circuito sob teste. Posteriormente, é desenvolvida uma metodologia de teste simples e com baixo custo, aplicável a Amplificadores Totalmente Diferenciais. Considerando a necessidade do Circuito de Realimentação de Modo Comum para manter o controle do modo comum das saídas, é proposta a reutilização deste circuito como verificador, possibilitando a observação de falhas ocorridas tanto no Amplificador quanto no próprio bloco de CMFB. Falhas catastróficas e paramétricas são injetadas, por simulação, em dois amplificadores totalmente diferenciais, um projetado em 180nm e outro em 130nm. Testes DC e transientes são realizados e a cobertura de falhas é avaliada. Os resultados das simulações apontam boa cobertura de falhas, enquanto apenas os sinais de realimentação de modo comum precisam ser monitorados. Dessa forma é proposta uma estratégia de teste que apresenta um baixo custo e uma baixa sobrecarga de área do circuito. / This work presents a study related to the testing of Differential Amplifiers. Firstly, by means of SPICE simulations, catastrophic faults are injected in two complementary Differential Amplifiers, designed considering a 0,5μm CMOS technology, in order to prove the concept of testing the circuit by checking the occurrence of variations in the DC voltage of the circuit internal nodes due to the injected faults. The possibility of diagnosing faults using a digitized representation of the DC values of the observed nodes of the circuit was also investigated. Then, a simple and cost-effective test methodology for Fully Differential Amplifiers (FDA) is proposed. Considering the need of the common mode feedback circuit to maintain the control of the common mode output voltage, it is proposed to re-use this circuit as a checker, allowing the observation of faults in both the amplifier itself and the CMFB block. Catastrophic and parametric faults are injected in two FDAs, designed in 180nm and 130nm technology respectively. DC and transient tests are performed and the fault coverage is evaluated. The simulation results indicate high fault coverage, while only the signals from the common mode feedback need to be monitored. This way a low cost and low overhead test methodology is proposed.

Este trabalho apresenta estudos voltados ao teste de Amplificadores Diferenciais. No primeiro momento, por meio de simulações SPICE, falhas catastróficas são injetadas em dois Amplificadores Diferenciais, projetados para uma tecnologia CMOS de 0,5m com configurações complementares, a fim de comprovar a ocorrência de variações nas tensões DC dos nós do circuito sob teste à medida que há injeções de falhas no mesmo. Também se faz análises preliminares dos resultados para verificar a possibilidade de diagnosticar as falhas através de assinaturas compostas pela digitalização (em um bit) dos valores DC dos nós do circuito sob teste. Posteriormente, é desenvolvida uma metodologia de teste simples e com baixo custo, aplicável a Amplificadores Totalmente Diferenciais. Considerando a necessidade do Circuito de Realimentação de Modo Comum para manter o controle do modo comum das saídas, é proposta a reutilização deste circuito como verificador, possibilitando a observação de falhas ocorridas tanto no Amplificador quanto no próprio bloco de CMFB. Falhas catastróficas e paramétricas são injetadas, por simulação, em dois amplificadores totalmente diferenciais, um projetado em 180nm e outro em 130nm. Testes DC e transientes são realizados e a cobertura de falhas é avaliada. Os resultados das simulações apontam boa cobertura de falhas, enquanto apenas os sinais de realimentação de modo comum precisam ser monitorados. Dessa forma é proposta uma estratégia de teste que apresenta um baixo custo e uma baixa sobrecarga de área do circuito. / This work presents a study related to the testing of Differential Amplifiers. Firstly, by means of SPICE simulations, catastrophic faults are injected in two complementary Differential Amplifiers, designed considering a 0,5μm CMOS technology, in order to prove the concept of testing the circuit by checking the occurrence of variations in the DC voltage of the circuit internal nodes due to the injected faults. The possibility of diagnosing faults using a digitized representation of the DC values of the observed nodes of the circuit was also investigated. Then, a simple and cost-effective test methodology for Fully Differential Amplifiers (FDA) is proposed. Considering the need of the common mode feedback circuit to maintain the control of the common mode output voltage, it is proposed to re-use this circuit as a checker, allowing the observation of faults in both the amplifier itself and the CMFB block. Catastrophic and parametric faults are injected in two FDAs, designed in 180nm and 130nm technology respectively. DC and transient tests are performed and the fault coverage is evaluated. The simulation results indicate high fault coverage, while only the signals from the common mode feedback need to be monitored. This way a low cost and low overhead test methodology is proposed.

Ultrawideband (UWB) phased antenna arrays are critical to the success of future multi-functional communication, sensing, and countermeasure systems, which will utilize a few UWB phased arrays in place of multiple antennas on a platform. The success of this new systems approach relies in part on the ability to manufacture and assemble low-cost UWB phased arrays with excellent radiation characteristics.This dissertation presents the theory and design of a new class of UWB arrays that is based on unbalanced fed tightly-coupled horizontal dipoles over a ground plane. Practical implementation of this concept leads to two inexpensive wideband array topologies, the Banyan Tree Antenna (BTA) Array, and the Planar Ultrawideband Modular Antenna (PUMA) Array. The key challenge in designing unbalanced-fed tightly-coupled dipole arrays lies in the control of a common mode resonance that destroys UWB performance. This work introduces a novel feeding strategy that eliminates this resonance and results in wideband, wide-angle radiation. More importantly, the new feeding scheme is simple and intuitive, and can be implemented at low-cost in both vertically and planarly-integrated phased array architectures. Another desirable byproduct of this topology is the electrical and mechanical modularity of the aperture, which enables easy manufacturability and assembly. A theoretical framework is presented for the new phased array topologies, which is then applied to the design of innite BTA and PUMA arrays that achieve 4:1 and 5:1 bandwidths,respectively. A practical application of this technology is demonstrated through the full design, fabrication, and measurement of a 7.25-21GHz 16x16 dual-pol PUMA array prototype for SATCOM applications.

Common mode performance is important for photovoltaic applications where the common mode voltage can become hazardous to people near the solar installation and can cause reliability concerns in inverters. The proposed dual-buck inverter uses hybrid unipolar modulation and a topology that is modified from the standard full-bridge dual-buck inverter to address the common mode voltage concerns. In the proposed design, the fast-switching side of the inverter is identical to a half-bridge dual-buck inverter, while the side that switches at line frequency uses a half-bridge of the standard H-bridge inverter topology. The motivation of this design is to realize the benefits of unipolar modulation and the dual-buck topology, while improving the poor common-mode voltage performance associated with unipolar modulation by utilizing hybrid switching. Unipolar switching has benefits which carry over to the hybrid switching scheme, such as reduced current ripple allowing use of smaller inductors. Additionally, the dual-buck topology enables the effective use of faster switches due to the elimination of dead time and reverse recovery concerns by using devices such as wide-bandgap GaN HEMTS and SiC Schottky diodes. The proposed inverter topology also realizes the benefits of the dual-buck topology while using half of the number of diodes and inductors compared to a standard full-bridge dual-buck inverter. The use of this modified dual-buck topology and hybrid unipolar modulation results in an inverter which has favorable common mode voltage characteristics. These characteristics indicate that this inverter would be useful in applications sensitive to common mode voltage concerns, such as photovoltaic applications. The performance of this topology using hybrid unipolar modulation is investigated using simulations and by creating and testing a 300-watt prototype inverter. / Master of Science / The popularity of photovoltaic panels has been increasing rapidly in recent years due to popular desire to reduce reliance on nonrenewable energy sources and steady reductions in the cost of solar power installations. The DC power provided by photovoltaic panels requires an inverter to create AC power to interface with the grid. However, in some scenarios the common-mode voltage can induce leakage current in the system, which can be hazardous to nearby people. Leakage current is larger for systems with high parasitic capacitance and for inverters that create high frequency components in their common mode voltage. Photovoltaic panels tend to have high parasitic capacitance, causing leakage current concerns. Additionally, advancements in wide bandgap devices enable inverters to operate at increasingly higher switching frequencies, and this is typically advantageous because it allows size reduction of expensive and heavy components used in inverter output filters. However, this can exacerbate leakage current concerns by introducing high frequency components to the common mode voltage. These developments create an incentive to investigate inverter designs that can mitigate leakage current concerns by creating favorable common mode voltage waveforms. Many existing solutions require circuit topologies with additional switches or use additional components like an isolation transformer or an additional common mode filter. These solutions add cost and complexity to inverter design. This thesis investigates a circuit topology based on a dual-buck inverter using hybrid unipolar switching, which will effectively utilize wide bandgap devices operating at high frequencies. The use of hybrid unipolar switching produces favorable common mode voltage characteristics that mitigates leakage current concerns while maintaining the quality of the output waveform, and the topology uses fewer diodes and inductors than a traditional dual-buck inverter. The design is evaluated through simulation and by creating and testing a 300-watt prototype to determine if it is suitable for photovoltaic applications and other applications where common mode voltage and leakage current are major concerns.

No description available.

As wide-bandgap devices continue to experience deeper penetration in commercial applications, there are still a number of factors which make the adoption of such technologies difficult. One of the most notable issues with the application of wide-bandgap technologies is meeting existing noise requirements and regulations. Due to the faster dv/dt and di/dt of SiC devices, more noise is generated in comparison to Si IGBTs. Therefore, in order to fully experience the benefits offered by this new technology, the noise must either be filtered or mitigated by other means. A survey of various DC/DC topologies was conducted in order to find a candidate for a battery interface in a UPS system. A three-level NPC topology was explored for its potential benefit in terms of noise, efficiency, and additional features. This converter topology was modeled, simulated, and a hardware prototype constructed for evaluation within a UPS system, although its uses are not limited to such applications. A UPS system is a good example of an application with strict noise requirements which must be fulfilled according to IEC standards. Based on a newly devised mode of operation, this converter was verified to produce no common-mode voltage under ideal conditions, and was able to provide a 6 dB reduction in common-mode voltage emissions in the UPS prototype. This was done while achieving a peak efficiency in excess of 99% with the ability to provide bidirectional power flow between the UPS and battery backup. The converter was verified to operate at the rated UPS conditions of 20 kW while converting between a total DC bus voltage of 800 V and a nominal battery voltage of 540 V. / Master of Science / As material advancements allow for the creation of devices with superior electrical characteristics compared to their predecessors, there are still a number of factors which cause these devices to see limited usage in commercial applications. These devices, typically referred to as wide-bandgap devices, include silicon carbide (SiC) transistors. These SiC devices allow for much faster switching speeds, greater efficiencies, and lower system volume compared to their silicon counterparts. However, due to the faster switching of these devices, there is more electromagnetic noise generated. In many applications, this noise must be filtered or otherwise mitigated in order to meet international standards for commercial use. Consequently, new converter topologies and configurations are necessary to provide the most benefit of the new wide-bandgap devices while still meeting the strict noise requirements. A survey of topologies was conducted and the modeling, design, and testing of one topology was performed for use in an uninterruptible power supply (UPS). This converter was able to provide a noticeable reduction in noise compared to standard topologies while still achieving very high efficiency at rated conditions. This converter was also verified to provide power bidirectionally—both when the UPS is charging the battery backup, and when the battery is supplying power to the load.