Recently, matrix converter has received considerable interest as a viable alternative to the conventional back-to-back PWM (Pulse Width Modulation) converter in the ac/ac conversion. This direct ac/ac converter provides some attractive characteristics such as: inherent four-quadrant operation; absence of bulky dc-link electrolytic capacitors; clean input power characteristics and increased power density. However, industrial application of the converter is still limited because of some practical issues such as common mode voltage effects, high susceptibility to input power disturbances and low voltage transfer ratio. This dissertation proposes several new matrix converter topologies together with control strategies to provide a solution about the above issues. In this dissertation, a new modulation method which reduces the common mode voltage at the matrix converter is first proposed. The new method utilizes the proper zero vector selection and placement within a sampling period and results in the reduction of the common mode voltage, square rms of ripple components of input current and switching losses. Due to the absence of a dc-link, matrix converter powered ac drivers suffer from input voltage disturbances. This dissertation proposes a new ride-through approach to improve robustness for input voltage disturbances. The conventional matrix converter is modified with the addition of ride-through module and the add-on module provides ride-through capability for matrix converter fed adjustable speed drivers. In order to increase the inherent low voltage transfer ratio of the matrix converter, a new three-phase high-frequency link matrix converter is proposed, where a dual bridge matrix converter is modified by adding a high-frequency transformer into dc-link. The new converter provides flexible voltage transfer ratio and galvanic isolation between input and output ac sources. Finally, the matrix converter concept is extended to dc/ac conversion from ac/ac conversion. The new dc/ac direct converter consists of soft switching full bridge dc/dc converter and three phase voltage source inverter without dc link capacitors. Both converters are synchronized for zero current/voltage switching and result in higher efficiency and lower EMI (Electro Magnetic Interference) throughout the whole load range. Analysis, design example and experimental results are detailed for each proposed topology.

Common mode performance is important for photovoltaic applications where the common mode voltage can become hazardous to people near the solar installation and can cause reliability concerns in inverters. The proposed dual-buck inverter uses hybrid unipolar modulation and a topology that is modified from the standard full-bridge dual-buck inverter to address the common mode voltage concerns. In the proposed design, the fast-switching side of the inverter is identical to a half-bridge dual-buck inverter, while the side that switches at line frequency uses a half-bridge of the standard H-bridge inverter topology. The motivation of this design is to realize the benefits of unipolar modulation and the dual-buck topology, while improving the poor common-mode voltage performance associated with unipolar modulation by utilizing hybrid switching. Unipolar switching has benefits which carry over to the hybrid switching scheme, such as reduced current ripple allowing use of smaller inductors. Additionally, the dual-buck topology enables the effective use of faster switches due to the elimination of dead time and reverse recovery concerns by using devices such as wide-bandgap GaN HEMTS and SiC Schottky diodes. The proposed inverter topology also realizes the benefits of the dual-buck topology while using half of the number of diodes and inductors compared to a standard full-bridge dual-buck inverter. The use of this modified dual-buck topology and hybrid unipolar modulation results in an inverter which has favorable common mode voltage characteristics. These characteristics indicate that this inverter would be useful in applications sensitive to common mode voltage concerns, such as photovoltaic applications. The performance of this topology using hybrid unipolar modulation is investigated using simulations and by creating and testing a 300-watt prototype inverter. / Master of Science / The popularity of photovoltaic panels has been increasing rapidly in recent years due to popular desire to reduce reliance on nonrenewable energy sources and steady reductions in the cost of solar power installations. The DC power provided by photovoltaic panels requires an inverter to create AC power to interface with the grid. However, in some scenarios the common-mode voltage can induce leakage current in the system, which can be hazardous to nearby people. Leakage current is larger for systems with high parasitic capacitance and for inverters that create high frequency components in their common mode voltage. Photovoltaic panels tend to have high parasitic capacitance, causing leakage current concerns. Additionally, advancements in wide bandgap devices enable inverters to operate at increasingly higher switching frequencies, and this is typically advantageous because it allows size reduction of expensive and heavy components used in inverter output filters. However, this can exacerbate leakage current concerns by introducing high frequency components to the common mode voltage. These developments create an incentive to investigate inverter designs that can mitigate leakage current concerns by creating favorable common mode voltage waveforms. Many existing solutions require circuit topologies with additional switches or use additional components like an isolation transformer or an additional common mode filter. These solutions add cost and complexity to inverter design. This thesis investigates a circuit topology based on a dual-buck inverter using hybrid unipolar switching, which will effectively utilize wide bandgap devices operating at high frequencies. The use of hybrid unipolar switching produces favorable common mode voltage characteristics that mitigates leakage current concerns while maintaining the quality of the output waveform, and the topology uses fewer diodes and inductors than a traditional dual-buck inverter. The design is evaluated through simulation and by creating and testing a 300-watt prototype to determine if it is suitable for photovoltaic applications and other applications where common mode voltage and leakage current are major concerns.

As wide-bandgap devices continue to experience deeper penetration in commercial applications, there are still a number of factors which make the adoption of such technologies difficult. One of the most notable issues with the application of wide-bandgap technologies is meeting existing noise requirements and regulations. Due to the faster dv/dt and di/dt of SiC devices, more noise is generated in comparison to Si IGBTs. Therefore, in order to fully experience the benefits offered by this new technology, the noise must either be filtered or mitigated by other means. A survey of various DC/DC topologies was conducted in order to find a candidate for a battery interface in a UPS system. A three-level NPC topology was explored for its potential benefit in terms of noise, efficiency, and additional features. This converter topology was modeled, simulated, and a hardware prototype constructed for evaluation within a UPS system, although its uses are not limited to such applications. A UPS system is a good example of an application with strict noise requirements which must be fulfilled according to IEC standards. Based on a newly devised mode of operation, this converter was verified to produce no common-mode voltage under ideal conditions, and was able to provide a 6 dB reduction in common-mode voltage emissions in the UPS prototype. This was done while achieving a peak efficiency in excess of 99% with the ability to provide bidirectional power flow between the UPS and battery backup. The converter was verified to operate at the rated UPS conditions of 20 kW while converting between a total DC bus voltage of 800 V and a nominal battery voltage of 540 V. / Master of Science / As material advancements allow for the creation of devices with superior electrical characteristics compared to their predecessors, there are still a number of factors which cause these devices to see limited usage in commercial applications. These devices, typically referred to as wide-bandgap devices, include silicon carbide (SiC) transistors. These SiC devices allow for much faster switching speeds, greater efficiencies, and lower system volume compared to their silicon counterparts. However, due to the faster switching of these devices, there is more electromagnetic noise generated. In many applications, this noise must be filtered or otherwise mitigated in order to meet international standards for commercial use. Consequently, new converter topologies and configurations are necessary to provide the most benefit of the new wide-bandgap devices while still meeting the strict noise requirements. A survey of topologies was conducted and the modeling, design, and testing of one topology was performed for use in an uninterruptible power supply (UPS). This converter was able to provide a noticeable reduction in noise compared to standard topologies while still achieving very high efficiency at rated conditions. This converter was also verified to provide power bidirectionally—both when the UPS is charging the battery backup, and when the battery is supplying power to the load.

Multilevel inverters play a major role in the modern day medium and high power energy conversion processes. The classic two level voltage source inverter generates PWM pole voltage output having two levels with strong fundamental component and harmonics centered around the switching frequency and its multiples. With higher switching frequency, its components can be easily filtered and results in better Total harmonic distortion (THD) output voltage and current. But with higher switching frequency, switching loss of power devices increases and electromagnetic interferences also increases. Also in two level inverter, pole voltage switches between zero and DC bus volt-age Vdc. This switching results in high dv=dt and causes EMI and increased stress on the motor winding insulation. The attractive features of multilevel inverters compared to a two level inverter are reduced switching frequency, reduced switching loss, improved volt-age and current THD, reduced dv=dt, etc. Because of these reasons, multilevel invertersultilevelinvertersplayamajorroleinthemoderndaymediumandhighpower find application in electric motor drives, transmission and distribution of power, transportation, traction, distributed generation, renewable energy systems like photo voltaic, hydel power, energy management, power quality, electric vehicle applications, etc. AC motor driven applications are consuming the significant part of the generated electrical energy (more than 60%) around the world. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low with lower out-put voltage dv=dt. Also by using multilevel inverters, the common mode voltage (CMV) switching can be made zero and associated motor bearing failure can be mitigated. For multilevel inverter topologies, as the number of level increases, the power circuit becomes more complex by the increase in the number of DC power supplies, capacitors, switching devices and associated control circuitry. The main focus of development in multilevel inverter for medium and high power applications is to obtain an optimized number of voltage levels with reduced number of switching devices, capacitors and DC power sources. In this thesis, a new hybrid seven level inverter topology with a single DC supply is proposed with reduced switch count. The inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. Compared to the conventional seven level inverter topologies, the proposed inverter topology uses lesser number of semiconductor devices, capacitors and DC power supplies for its operation. For this topology, capacitor voltage balancing is possible for entire modulation range irrespective of the load power factor. Also capacitor voltage can be controlled over a switching cycle and this result in lowering the capacitor sizing for the proposed topology. A simple hysteresis band based capacitor voltage balancing scheme is implemented for the inverter topology. For a voltage source inverter fed induction motor drive system, the inverter pole voltage is the sum of motor phase voltage and common mode voltage. In induction motors, there exists a parasitic capacitance between stator winding and stator iron, and between stator winding and rotor iron. Common mode voltage with significant magnitude and high frequency switching causes leakage current through these parasitic capacitances and motor bearings. This leakage current can cause ash over of bearing lubricant and corrosion of ball bearings, resulting in an early mechanical failure of the drive system. In this thesis, analysis of extending the linear modulation range of a general n-level inverter by allowing reduced magnitude of common mode voltage (CMV) switching (only Vdc/18) is presented. A new hybrid seven level inverter topology, with a single DC supply and with reduced common mode voltage (CMV) switching is presented in this thesis for the first time. Inverter is operated with zero CMV for modulation index less than 86% and is operated with a CMV magnitude of Vdc/18 to extend the linear modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilizing the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology. In recent years, model predictive control (MPC) using the system model has proved to be a good choice for the control of power converter and motor drive applications. MPC predicts system behavior using a system model and current system state. For cascaded multilevel inverter topologies with a single DC supply, closed loop capacitor voltage control is necessary for proper operation. This thesis presents zero and reduced common mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state which minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96% the inverter can operate with reduced CMV magnitude ( Vdc/18) and reduced CMV switching frequency using the new space-vector PWM (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme. The operation of a two level inverter in the over-modulation region (maximum peak phase fundamental output of inverter is greater than 0:577Vdc) results in lower order harmonics in the inverter output voltage. This lower order harmonics (mainly 5th, 7th, 11th, and 13th) causes electromagnetic torque ripple in motor drive applications. Also these harmonics causes extra losses and adversely affects the efficiency of the drive system. Also inverter control becomes non linear and special control algorithms are required for inverter operation in the over modulation region. In conventional schemes, maximum fundamental output voltage possible is 0:637Vdc. In that case inverter is operated in a square wave mode, also called six-step mode. This operation results in high dv=dt for the inverter output voltage. With multilevel inverters also, the inverter operation with peak phase fundamental output voltage above 0:577Vdc results in lower order harmonics in the inverter output voltage and results in electromagnetic torque pulsation. In this thesis, a new space vector PWM (SVPWM) method to extend the linear modulation range of a cascaded five level inverter topology with a single DC supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0:577Vdc to 0:637Vdc without increasing the DC bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0 Hz to 50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The ve level topology presented in this thesis is realized by cascading a two level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady state and dynamic operating conditions are presented. Zero common mode voltage (CMV) operation of multilevel inverters results in reduced DC bus utilization and reduced linear modulation range. In this thesis two reduced CMV SVPWM schemes are presented to extend the linear modulation range by allowing reduced CMV switching. But using these SVPWM schemes the peak phase fundamental output voltage possible is only 0:55Vdc in the linear region. In this thesis, a method to extend the linear modulation range of a CMV eliminated hybrid cascaded multilevel inverter with a single DC supply is presented. Using this method peak fundamental voltage can be increased from 0 to 0:637Vdc with zero CMV switching inside the linear modulation range. Also inverter can be controlled linearly for the entire modulation range. Also, various PWM switching sequences are analyzed in this thesis and the PWM sequence which gives minimum current ripple is used for the zero CMV operation of the inverter. The inverter topology with single DC supply is realized by cascading a two level inverter with two floating capacitor fed full bridge modules. Simulation and experimental results for steady state and dynamic operating conditions are presented to validate the proposed method. A three phase, 400 V, 3.7 kW, 50 Hz, two-pole induction motor drive with the open-loop V/f control scheme is implemented in the hardware for testing proposed inverter topology and proposed SVPWM algorithms experimentally. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V IGBT half-bridge modules (SKM-75GB-12T4). Optoisolated gate drivers with de-saturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation, TMS320F28335 DSP is used as the main controller and Xilinx SPARTAN-3 XC3S200 FPGA as the PWM signal generator with dead time of 2.5 s. Level shifted carrier-based PWM algorithm is implemented for the normal inverter operation and zero CMV operation. From the PWM algorithm, information about the pole voltage levels to be switched can be obtained for each phase. In the sampling period, for capacitor voltage balancing of each phase, the DSP selects a switching state using the capacitor voltage information, current direction and pole voltage data for each phase. This switching state information along with the PWM timing data is sent to an FPGA module. The FPGA module generates the gating signals with a dead time of 2.5 s for the gate driver module for all the three phases by processing the switching state information and PWM signals for the given sampling period. For fundamental frequencies above 10Hz, synchronous PWM technique was used for testing the inverter topology. For modulation frequencies 10Hz and below, a constant switching frequency of 900 Hz was used. Various steady state and transient operation results are provided to validate the proposed inverter topology and the zero and reduced CMV operation schemes and extending the linear modulation scheme presented in this thesis. With the advantages like reduced switch count, single DC supply requirement, zero and reduced CMV operation, extension of linear modulation range, linear control of induction motor over the entire modulation range with zero CMV, lesser dv=dt stresses on devices and motor phase windings, lower switching frequency, inherent capacitor balancing, the proposed inverter power circuit topologies, and the SVPWM methods can be considered as good choice for medium voltage, high power motor drive applications.

Due to modularity and easy scalability, modular multilevel converters (MMCs) are deemed the most suitable for high-voltage and medium-voltage power conversion applications. However, large module capacitors are usually required in MMCs to store large circulating power of line-frequency and its harmonics that flow through the capacitors. Even though several methods for minimizing the circulating power have been proposed in the literature, there is still the need for a systematic and simplified approach of addressing these control strategies and evaluating their efficacy. Moreover, the generally accepted feedback control architecture for the MMC is complicated, derived through a rigorous mathematical analysis, and therefore, not easy to intuitively comprehend. Recently, a method of modeling of the MMC based on state-plane analysis and coordinate transformation, is proposed in the literature. Based on the state-plane analysis, two kinds of circulating power in the MMC are identified that are orthogonal to each other. This means these two circulating power can be controlled individually without affecting each other. To control these circulating power, in the literature, a decoupled equivalent circuit model is developed through the coordinate transformation which clearly suggests a means for minimizing these circulating power. Further extending this work, in this thesis, the existing control concepts for reducing the circulating power are unveiled in a systematic and simplified manner utilizing the decoupled equivalent circuit model. A graphical visualization of circulating power using the state-planes is provided for each control strategy to readily compare its efficacy. Moreover, the generally accepted control architecture of the MMC is presented in an intuitive and simplified way using the decoupled circuit model. The important physics related to control implementation, originally hidden behind the complicated mathematics, is explained in detail. / Master of Science / A power converter is an electrical device that converts electrical energy from one form to another in order to be compatible with the load demand. A typical power converter consists of semiconductor switches, inductor, capacitor etc. These power converters are required in a wide range of applications: automotive and traction, motor drives, renewable energy conversion, energy storage, aircraft, power generation, transmission, and distribution, to name a few. Many of these applications are continuously increasing their power capacity to handle the escalating demands of energy that exist due to rising population numbers, industrialization, urbanization etc. Consequently, it has been a responsibility of power electronics engineers and researchers to develop power converters that can handle high voltages and high currents. Multilevel power converters have been the key-enabling developments that can withstand high-voltages while using traditional low-voltage semiconductor switches. Several multilevel converters such as the neutral point clamped converter, flying capacitor converter, cascaded H-bridge converter, modular multilevel converter (MMC) etc. have been developed and commercialized in the last two decades. Among them, the MMC is a widely accepted topology for medium- and high-voltage power conversion applications. In an MMC, several modules are stacked together in series, and each module consists of semiconductor switches and a capacitor. The series connection of the modules enables the MMC to handle high-voltage power conversion using low-voltage traditional semiconductor switches. The voltage rating of an MMC can be easily scaled-up by simply increasing the number of modules in each arm. Moreover, since several identical modules are connected in each arm, the structure of the MMC is highly modular which helps greatly in manufacturing and design. Nonetheless, in MMCs, generally large circulating power flow to the capacitor in each module, which leads to significant voltage ripples. To suppress these voltage ripples, a large capacitor is required in each module, leading to large size and weight of the converter. In the literature, several control strategies have been proposed to minimize the circulating power. However, there is still the need for a systematic and simplified approach of addressing these control strategies and evaluating their efficacy. Moreover, the generally accepted feedback control architecture for the MMC is complicated, derived through a rigorous mathematical analysis, and therefore, not easy to intuitively comprehend. Recently, a decoupled equivalent circuit model has been developed in the literature. This model clearly explains the process of power flow in the MMC between input and output and the nature of the circulating power. The equivalent circuit model provides the circulating power, that are orthogonal to each other, meaning they can be controlled individually without affecting each other. Moreover, the equivalent circuit model clearly suggests a means for minimize the circulating power by providing two "ideal" control laws. Further extending this work, in this thesis, the existing control concepts for reducing the circulating power are unveiled in a systematic and simplified manner utilizing the decoupled equivalent circuit model. Moreover, the generally accepted control architecture of the MMC is presented in an intuitive and simplified way via the decoupled circuit model. The important physics related to control implementation, originally hidden behind the complicated mathematics, is explained in detail.

The trend in power electronics converters is to be highly efficient, compact, reliable, and cost-effective. Conventionally, power converters supply or consume power from the low-voltage utility, which impacts the size and efficiency of the system. For example, the recent proliferation of electric vehicles has demanded the rapid installation of dc fast chargers (DCFC) across the country. However, most of the commercial DCFCs operate at 480 V transferring hundreds of kilowatts, resulting in large line currents which could hinder the size, cost, and efficiency of conventional DCFCs. Conversely, modular multilevel power topologies can be directly tied to the medium-voltage (MV) grid, eliminating the line-frequency transformer and the bulky line cable requirements. Among these topologies, the cascaded H-bridge (CHB) has been extensively used in the industry for MV-high-power applications because of its cost and efficiency in this operation range. Thus, it is one of the prevalent topologies for MV solid-state transformers (SSTs) The asymmetrical hybrid binary CHB (HBCHB) allows increased output voltage levels at the expense of modularity. Based on the HBCHB, a converter new modular topology regarded as the pseudo-binary CHB (PBCHB) is proposed for the ac-dc front-end stage SSTs. To operate the PBCHB, a new hybrid modulator is developed to operate the three modular structures of the PBCHB with step-like sinusoidal waveforms at near-line-frequency commutations while an asymmetrical floating capacitor (FC) module operates at high-frequency PWM commutation. The FC module does not transfer active power but serves only as a power quality enhancer of the PBCHB. However, the modular structures symmetrically transfer all the power from the MV grid to the load. With the SST structure of the PBCHB, the dc-link voltages of the H-bridges are naturally balanced; yet the proposed hybrid modulator enables equal power transfer in the three modular structures. In addition, a controller for the FC voltage is designed, analyzed, and implemented in the proposed hybrid modulator The effectiveness of the proposed front-end SST with the proposed modulation and control technique is verified in a 1.2 kV/3 kW single-phase prototype, where each module was able to transfer 1kW each. Electromagnetic interference (EMI) also impacts the cost, size, and reliability of three-phase systems because they may require bulky EMI filters to avoid self-pollution and polluting the grid. The common-mode voltage (CMV) is one important factor of EMI emissions. Thus, reducing or eliminating it could improve the cost and size of the system. Space vector pulsewidth modulation (SVWPM) can directly design the CMV output and the switching sequence of three-phase converters. However, its implementation can become complex in converters with many levels such as MV grid-tied SST converters. This dissertation uses the digital gh coordinate and proposes a set of computations to easily retrieve the converter states with a reduced CMV and generate a symmetrical switching sequence with reduced number of commutations. To do this, a single vector among the nearest three vectors (NTVs) is sufficient to implement the switching sequence for the reduced commutation and reduced CMV SVPWM. Additionally, the dc bus can be fully utilized. Unlike conventional approaches, the developed technique is easily scalable because its computational complexity does not depend on the number of levels of the converter. The proposed reduced CMV technique was verified in a three-phase 15-level 311 V/600 W unit. Moving forward in the objective of CMV reduction, a new jk-coordinate system for multilevel converters is proposed for SVPWM with eliminated CMV. With the jk coordinates, the converter states that yield zero CMV (ZCMV) can be directly computed. In addition, a single jk vector is sufficient to generate the switching sequences of NTVs. Moreover, the switching sequences feature reduced losses for high-power-factor applications in the phase that naturally commutes twice during a sampling period. Similarly, the computation burden of the ZCMV SVPWM technique presented in this dissertation is not affected by the number of levels of the converter, thus, it is scalable. The three-phase 15-level 311 V/600 W prototype was utilized to verify this technique. / Doctor of Philosophy / The recent demands for fast chargers for electric vehicles (EV), photovoltaic (PV) energy integration, and data centers for artificial intelligence (AI) have driven the research and development of efficient, compact, and cost-effective power electronic solutions. Under these motivations, the solid-state transformer (SST) is a power electronics configuration that can benefit the EV, PV, AI, and several other applications. By eliminating the requirement of a line-frequency transformer, SSTs can be directly connected to the medium-voltage (MV) grid, reducing the weight and volume, and improving efficiency. The main reason for these advantageous attributes is the utilization of multilevel ac/dc or dc/ac converters. Among these, the cascaded H-bridge (CHB) converter has been extensively used in the industry for MV-high-power applications because of its cost, fault tolerance, and efficiency, making it a favorable converter for MV SSTs. Symmetrical modules in the CHB must commutate at the same pulsewidth modulation (PWM) when operating in an SST. An asymmetrical configuration such as the hybrid binary CHB (HBCHB) allows increased output voltage levels and low-frequency commutation at the expense of modularity. This dissertation proposes a pseudo-binary CHB (PBCHB) inspired by the HBCHB to obtain low-frequency commutations, thus, negligible switching losses in the SST. The PBCHB has symmetrical modules that transfer balanced active power with negligible switching losses while an asymmetrically smaller module enhances the power quality with PWM operation. To do this, a new hybrid modulator and controller were designed, analyzed, and verified in this dissertation. The effectiveness of the proposed front-end PBCHB-based SST with the developed modulation and control techniques is verified in an MV 1.2 kV/3 kW single-phase prototype. Electromagnetic interference (EMI) filters can impact the cost, size, and reliability of SSTs. The common-mode voltage (CMV) that power converters generate is one type of EMI emissions that could impact the cost and size of the system. The modulation technique called space vector pulsewidth modulation (SVWPM) has the freedom to design a switching sequence able to reduce or eliminate the CMV. However, implementing the SVPWM can become complex in MV grid-tied SST converters (PBCHB, CHB, HBCHB) with many voltage levels. This dissertation uses the digital gh coordinate system and a new jk coordinate system to reduce and eliminate the CMV, respectively. These coordinates systems have the advantage of reduced computational complexity in multilevel converters with large number of output voltage levels increases. The proposed techniques can retrieve back the abc signals for the PWM drivers without repetitive iterations. Moreover, the proposed techniques can generate symmetrical switching sequences with reduced number of commutations and switching losses in the converter. To do this, the computation of a single vector among the nearest three vectors is sufficient to implement the switching sequences of SVPWM. As a result, the computational complexity of the SVPWM techniques in this dissertation is constant and does not vary with the number of output voltage levels, making them easily scalable solutions compared to previous solutions in the literature. The proposed reduced and eliminated CMV SVPWM techniques were verified in a three-phase 15-level 311 V/600 W HBCHB unit in inverting mode.

Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. Voltage operation above semiconductor device limits, lower common mode voltages, near sinusoidal outputs together with small dv/dt’s, are some of the characteristics that have made this power converters popular for industry and modern research. However, the existing solutions suffer from some inherent drawbacks like common mode voltage problem, DC-link capacitor voltage fluctuation etc. Cascaded multi-level inverter with open-end winding induction motor structure promises significant improvements for high power medium-voltage applications. This dissertation investigates such cascaded multi-level inverters for open-end winding induction motor drive with reduced switch count. Similar to the conventional two-level inverters, other multi-level inverters with PWM control generate alternating common mode voltage (CMV). The alternating common mode voltage coupled through the parasitic capacitors in the machine and results in excessive bearing current and shaft voltage. The unwanted shaft voltage may cross the limit of insulation breakdown voltage and cause motor failure. This alternating common mode voltage adds to the total leakage current through ground conductor and acts as a source of conducted EMI which can interfere with other electronic equipments around. As the number of level increase in the inverter, different voltage levels are made available by using DC-link capacitor banks, instead of using different isolated power supplies. The intermediate-circuit capacitor voltages which are not directly supplied by the power sources are inherently unstable and require a suitable control method for converter operation, preferably without influence on the load power factor. Apart from normal operation, the sudden fault conditions may occur in the system and it is necessary to implement the control strategy considering this condition also. A five-level inverter topology with cascaded power circuit structure is proposed in this dissertation with the strategy to eliminate the common mode voltage and also to maintain the balance in the DC-link capacitor voltages. The proposed scheme is based on a dual five-level inverter for open-end winding induction motor. The principle achievement of this work is the reduction of power circuit complexity in the five-level inverter compared to a previously proposed five-level inverter structure for open-end winding IM drive with common mode voltage elimination. The reduction in the number of power switching devices is achieved by sharing the two two-level inverters for both the inverter structures. The resultant inverter structure can produce a nine-level voltage vector structure with the presence of alternating common mode voltage. The inverter structure is formed by cascading conventional two-level inverters together with NPC three-level inverters. Thus it offers modular and simpler power bus structure. As the power circuit is realised by cascading conventional two-level and NPC three-level inverters the number of power diodes requirements also reduced compared to the conventional NPC five-level inverters. The present proposed structure is implemented for the open-end winding induction motor and the power circuit offers more number of switching state redundancies compared to any conventional five-level inverter. The inverter structure required half the DC-link voltage compared to the DC-link voltage required for the conventional five-level inverter structure for induction motor drive and this reduces the voltage stress on the individual power devices. The common mode voltage is eliminated by selecting only the switching states which do not generate any common mode voltage in pole voltages hence there will be no common mode voltage at the motor phase also. The technique of using the switching state selection for the common mode voltage elimination, cancels out the requirement of the filter for the same purpose. As the inverter output is achieved without the presence of common mode voltage, the dual inverter can be fed from the common DC-link sources, without generating any zero sequence current. Hence the proposed dual five-level inverter structure requires only four isolated DC supplies. The multi-level inverters supplied by single power supply, have inherent unbalance in the DC-link capacitor voltages. This unbalance in the DC-link capacitor voltages causes lower order harmonics at the inverter output, resulting in torque pulsation and increased voltage stress on the power switching devices. A five-level inverter with reduced power circuit complexity is proposed to achieve the dual task of eliminating common mode voltage and DC-link capacitor voltage balancing. The method includes the analysis of current through the DC-link capacitors, depending on the switching state selections. The conditions to maintain all the four DC-link capacitor voltages are analysed. In an ideal condition when there is no fault in the power circuit the balance in the capacitor voltages can be maintained by selecting switching states in consecutive intervals, which have opposite effect on the capacitor voltages. This is called the open loop control of DC-link capacitor voltage balancing, since the capacitor voltages are not sensed during the selection of the switching states. The switching states with zero common mode voltages are selected for the purpose of keeping the capacitor voltages in balanced condition during no fault condition. The use of any extra hardware is avoided. The proposed open loop control of DC-link capacitor voltage balancing is capable of keeping the DC-link capacitor voltages equal in the entire modulation region irrespective of the load powerfactor. The problem with the proposed open loop control strategy is that, it can not take any corrective action if there is any initial unbalance in the capacitor voltages or if any unbalance occurs in the capacitor voltages during operation of the circuit,. To get the corrective action in the capacitor voltages due occurrence of any fault in the circuit, the strategy is further improved and a closed loop control strategy for the DC-link capacitor voltages is established. All the possible fault conditions in the four capacitors are identified and the available switching states are effectively used for the corrective action in each fault condition. The strategy is implemented such a way that the voltage balancing can be achieved without affecting the output fundamental voltage. The proposed five-level inverter structure presented in this thesis is based on a previous work, where a five-level inverter structure is proposed for the open-end winding induction motor. In that previous work 48 switches are used for the realization of the power circuit. It is observed that all the available switching states in this previous work are not used for any of the performance requirement of CMV elimination or DC-link voltage balancing. So, in this proposed work, the power circuit is optimized by reducing some of the switches, keeping the performance of the inverter same as the power circuit proposed in the previous work. The five-level inverter proposed in this thesis used 36 switches and the number of switching states is also reduced. But, the available switching states are sufficient for the CMV elimination and DC-link capacitor voltage balancing. The advantage of the modular circuit structure of this proposed five-level inverter is further investigated and the inverter structure is modified to a seven-level inverter structure for the open end winding induction motor. The proposed power circuit of the seven-level inverter uses only 48 switches, which is less compared to any seven-level inverter structure for the open end winding induction motor with common mode voltage elimination. The power circuit is reduced by sharing four two-level inverters to both the individual seven-level inverters in both the sides of the of the open end winding induction motor. The cascaded structure eliminates the necessity of the power diodes as required by the conventional NPC multilevel inverters. The proposed seven-level inverter is capable of producing a thirteen-level voltage vector hexagonal structure with the presence of common mode voltage. The common mode voltage elimination is achieved by selecting only the switching states with zero common mode voltage from both the inverters and the combined inverter structure produce a seven-level voltage vector structure with zero common mode voltage. The switching frequency is also reduced for the seven-level inverter compared to the proposed five-level inverter. The advantage of this kind of power circuit structure is that the number of power diode requirement is same in both five-level and seven-level inverters. Since there is no common mode voltage in the output voltages, the dual seven-level inverter structure can be implemented with the common DC-link voltage sources for both the sides. Six isolated power supplies are sufficient for both the seven-level inverters. The available switching states in this proposed seven-level inverter are further analysed to implement the open loop and closed loop capacitor voltage balancing and this allow the power circuit to run with only three isolated DC supplies. All the proposed work presented in this thesis are initially simulated in SIMULINK toolbox and then implemented in a form of laboratory prototype. A 2.5KW open end winding induction motor is used for the implementation of these proposed works. But all these work general in nature and can be implemented for high power drive applications with proper device ratings.

Le travail de cette thèse apporte une contribution aux méthodes de réglage de la tension dans les réseaux électriques. Il s’agit de fournir au réseau la puissance active et surtout la puissance réactive nécessaire pour réguler la tension et aboutir à un système équilibré vue du côté source. Ces puissances sont extraites d’une source d’energie renouvelable : une attention particulière a été portée à l’énergie éolienne raccordée au réseau à travers la Machine Asynchrone à Double Alimentation (MADA) pilotée par des convertisseurs statiques. Le système de contrôle le plus répandu des éoliennes est basé principalement sur la technique d’extraction du maximum de puissance. Cependant, cette technique limite la mise en oeuvre deservices auxiliaires, telle que la participation des éoliennes au réglage de la tension dans le réseau électrique. Pour cela, une nouvelle méthode d’extraction du coefficient de puissance optimal, permettant d’améliorer la participation de la MADA à la régulation de la tension dans le réseau (compensation de la puissance réactive et du déséquilibre), a été développée. Le convertisseur multiniveaux à structure NPC (Neutral Point Clamped) raccordant l’énergie renouvelable au réseau a été étudié. La commande prédictive assurant simulatnément l’amélioration du facteur de puissance, l’équilibrage du réseau électrique et du bus continu du convertisseur NPC a été proposée. Ensuite, l’application de cette commande prédictive a été elargie en lui attribuant plusieurs objectifs : amélioration du facteur de puissance avec équilibrage du réseau, équilibrage du bus continu, minimisation des pertes par commutation et réduction de la tension de mode commun. La minimisation des pertes a été obtenue en proposant une nouvelle stratégie qui consiste à exploiter les datasheets constructeurs donnant l’évolution de l’énergie dissipée durant la commutation en fonction du courant. Ces courbes expérimentales ont été transformées en modèlesmathématiques implémentés dans la commande prédictive. Les résultats de simulation et expérimentaux sont présentés pour évaluer les performances de la méthode proposée. / The work in this research thesis presents a contribution to voltage regulation in electrical networks. By considering adequate active and reactive powers injection into the grid, voltage control and load balancing are provided. These powers are generated from a grid connected renewable energy conversion system : a special attention was paid to the Wind Energy ConversionSystem (WECS) based on Doubly-Fed Induction Generator (DFIG).The typical control strategy for WECS is the maximum power coefficient tracking method. However, this method limits desirable ancillary power services, such as the participation of wind turbines in voltage regulation in the power grid. Therefore, a new method that derives the optimal power coefficient enhancing the participation of WTS in voltage regulation in the network (reactive and unbalanced power compensation), has been developed. The multilevel NPC (Neutral Point Clamped) converter, used for grid interface connection of renewable energy sources systems, has been studied. A predictive control method for the three-level NPC converter, capable of simultaneously compensating the problems of : DC link capacitors voltage balancing, load balancing and power factor correction in the power system, has been proposed. Then, the application of this predictive control was extended to simultaneously achieve multiple objectives: load balancing with power factor correction in the network, DC link capacitors voltage balancing, switching losses minimization and common mode voltage reduction. The switching losses minimization was obtained by proposing a new strategy which consists on exploiting the manufacturer datasheets that gives the evolution of the switching loss energy in function of the circulating current. The experimental curves of the datasheet are expressed in a mathematical model implemented in the predictive control. Simulation and experimental results are presented to evaluate the performance of the proposed method.

Durant ces dernières années, l'intérêt pour les technologies des véhicules à faibles émissions de carbone a fait un bond important à travers l'Union européenne (UE) et au-delà, encouragé en cela par les gouvernements et les constructeurs automobiles. De grands espoirs ont été mis plus récemment dans les véhicules électriques (VE) et les véhicules électriques hybrides (VEH) en tant que technologies clés pour atténuer le changement climatique, améliorer la sécurité énergétique et favoriser une nouvelle branche de l'industrie dans le secteur automobile. Ainsi, l'électrification des transports a été considérée comme une stratégie clé pour réduire les émissions de CO2 dans le secteur des transports. Le principal défi est d’augmenter l’autonomie des véhicules (ce qui a toujours été au coeur de la concurrence des industries du transport), ainsi que la durée de vie des volumineuses et coûteuses batteries. Par conséquent, ceci indique que le rendement du convertisseur de puissance est un des points clés à développer pour les générations des véhicules électriques à venir. L’autre paramètre influant est la qualité de la tension et du courant (en particulier la suppression des harmoniques basses fréquences) qui permet de réduire la taille des filtres d'entrée et de sortie de ces convertisseurs. L'objectif de cette thèse est de parvenir à un meilleur rendement en proposant de nouvelles structures de convertisseur de puissance et des commandes vectorielles modifiées ; le choix de deux onduleurs alimentant un moteur ouvert aux deux extrémités. Après l'analyse étape par étape, modèle théorique, simulation et enfin une mise en oeuvre expérimentale, il a été constaté que les nouvelles méthodes proposées sont compétitives et peuvent s’appliquer aux cas des VEH et des VE afin d’apporter des caractéristiques supérieures en termes d’efficacité et de qualité de tension et de courant. / Over the last decade, the interest for low-carbon vehicle technologies has surged among both governments and automotive manufacturers across and beyond the European Union (EU). Great hopes have been put, first, on biofuel vehicles and more recently on electric vehicles (EVs) and hybrid electric vehicles (HEVs) as key technologies to mitigate climate change, enhance energy security and nurture new industry branches within the automotive sector. So electrification of vehicles has been seen as a key strategy to reduce CO2 emissions from the transport sector. The main challenge toward EVs and HEVs is to keep driving for longer distance (which has been always fields for competition among traction industries) as well as lifetime battery cells as storage system. As a result, these indicate importance of power converter efficiency as a key gate for next generations of these up-coming vehicles. The next parameter is the quality of output voltage/current (especially by suppressing low-order harmonics) to reduce the size of filtering. The aim of this thesis is to achieve better efficiency and output voltage/current Total Harmonic Distortion (THD) by proposing novel power converter and associated Pulse Width Modulation (PWM) methods while imposing modification on power converter topology. As a result, dual-inverter is proposed to supply open-end motor from both sides. To this aim, three PWM methods are suggested as: The first one, Modified Space Vector Modulation (MSVM) for dual-inverter supplied by single dc source, improves efficiency by 4-5% (while having lower switching losses), and reduces Common Mode Voltage (CMV) levels by 66%, as well. The voltage/current harmonics are analytically analyzed which shows mainly better performance. Effective switching frequency is also reduced by 66% due to the reduction of number of commutations. In the second one, Near State PWM (NSPWM) is adapted for dual-inverter supplied by single dc source in order to eliminate triplen harmonics (therefore Zero Sequence Voltage, ZSV) and improve efficiency (by 3-4%) compared to Space Vector Modulation (SVM). Additionally due to avoiding use of zero vectors, CMV is improved by 66%. While having 8 commutations instead of 12 in SVM, effective switching frequency is improved by 33%. And finally, the third proposed method deals with NSPWM for dual-inverter supplied by two isolated dc sources wherein efficiency and CMV levels show the same performance as previous one. However, in this method, voltage THD is highly reduced compared to SVM. Triplen harmonics of the output voltage are inherently suppressed by the structure. These 3 proposed methods are analytically studied and their performances are step by step simulated in Matlab/Simulink environment. Then the methods are implemented in dualinverter fed open-end motor in laboratory setup; and the results are compared with these of SVM. Finally, it is found that novel proposed methods are so competitive solutions to be applied in HEVs and EVs and bring superior efficiency and voltage/current harmonic features.