IEEE 802.11 wireless LANs operating in the infrastructure mode are extremely popular and have seen widespread deployment because of their convenience and cost efficiency. A large number of research studies have investigated the performance of DCF, the default MAC protocol in 802.11 WLANs. Previous studies have pointed out several performance problems caused by the interaction of DCF in infrastructure-based WLANs. This thesis addresses a few of these issues. In the first part of the thesis, we address the issue of head-of-line (HOL) blocking at the Access Point (AP) in infrastructure WLANs. We use a cooperative ARQ scheme to resolve the obstruction at the AP queue. We analytically study the performance of our scheme in a single cell IEEE 802.11 infrastructure WLAN under a TCP controlled file download scenario and validate our analysis by extensive simulations. Both analysis and simulation results show considerable increase in system throughput with the cooperative ARQ scheme. We further examine the delay performance of the ARQ scheme in the presence of both elastic TCP traffic and delay sensitive VoIP traffic. Simulations results show that our scheme decreases the delay in the downlink for VoIP packets significantly while simultaneously providing considerable gains in the TCP download throughput. Next, we propose a joint uplink/downlink opportunistic scheduling scheme for maximising system throughput in infrastructure WLANs. We first solve the uplink/downlink unfairness that exists in infrastructure WLANs by maintaining a separate queue and a backoff timer at the AP for each mobile station (STA). We also increase the system throughput by making the backoff timer a function of the channel gains. We analyse the I performance of our scheme under symmetric UDP traffic with i. i. d. channel conditions. Finally, we discuss several opportunistic scheduling policies which aim to increase the system throughput while satisfying certain Quality of Service (QoS) objectives. The standard IEEE 802.11 DCF protocol only offers best-effort services and does not provide any QoS guarantees. Providing QoS in 802.11 networks with time varying channel conditions has proven to be a challenge. We show by simulations that by an appropriate choice of the scheduling metric in our opportunistic scheduling scheme, different QOS objectives like maximizing weighted system sum throughput, minimum rate guarantees and throughput optimality can be attained.

Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.

Motivated by the increasing demand for higher data rates, coverage, and spectral efficiency, current and next generation wireless systems adapt transmission parameters and even who is being transmitted to, based on the instantaneous channel states. For example, frequency-domain scheduling(FDS) is an instance of adaptation in orthogonal frequency division multiple access(OFDMA) systems in which the base station opportunistically assigns different subcarriers to their most appropriate user. Likewise ,transmit antenna selection(AS) is another form of adaptation in which the transmitter adapts which subset of antennas it transmits with. Cognitive radio(CR), which is a next generation technology, itself is a form of adaptation in which secondary users(SUs) adapt their transmissions to avoid interfering with the licensed primary users(PUs), who own the spectrum. However, adaptation requires channel state information(CSI), which might not be available apriori at the node or nodes that are adapting. Further, the CSI might not be perfect due to noise or feedback delays. This can result in suboptimal adaptation in OFDMA systems or excessive interference at the PUs due to transmissions by the SUs in CR. In this thesis, we focus on adaptation techniques in current and next generation wireless systems and evaluate the impact of CSI –both perfect and imperfect –on it. We first develop a novel model and analysis for characterizing the performance of AS in frequency-selective OFDMA systems. Our model is unique and comprehensive in that it incorporates key LTE features such as imperfect channel estimation based on dense, narrow band demodulation reference signal and coarse, broad band sounding reference signal. It incorporates the frequency-domain scheduler, the hardware constraint that the same antenna must be used to transmit over all the subcarriers that are allocated to a user, and the scheduling constraint that the allocated subcarriers must all be contiguous. Our results show the effectiveness of combined AS and FDS in frequency-selective OFDMA systems even at lower sounding reference signal powers. We then investigate power adaptation in underlay CR, in which the SU can transmit even when the primary is on but under stringent interference constraints. The nature of the interference constraint fundamentally decides how the SU adapts its transmit power. To this end, assuming perfect CSI, we propose optimal transmit power adaptation policies that minimize the symbol error probability of an SU when they are subject to different interference and transmit power constraints. We then study the robustness of these optimal policies to imperfections in CSI. An interesting observation that comes out of our study is that imperfect CSI can not only increase the interference at the PU but can also decrease it, and this depends on the choice of the system parameters, interference, and transmit power constraints. The regimes in which these occur are characterized.

This thesis addresses the design of low-complexity coding schemes for wireless relay networks and multiple access channels. The first part of the thesis is on wireless relay networks and the second part is on multiple access channels. Distributed space-time coding is a well known technique to achieve spatial diversity in wireless networks wherein, several geographically separated nodes assist a source node to distributively transmit a space-time block code (STBC) to the destination. Such STBCs are referred to as Distributed STBCs (DSTBCs). In the first part of the thesis, we focus on designing full diversity DSTBCs with some nice properties which make them amenable for implementation in practice. Towards that end, a class of full diversity DST-BCs referred to as Co-ordinate Interleaved DSTBCs (CIDSTBCs) are proposed for relay networks with two-antenna relays. To construct CIDSTBCs, a technique called co-ordinate vector interleaving is introduced wherein, the received signals at different antennas of the relay are processed in a combined fashion. Compared to the schemes where the received signals at different antennas of the relay are processed independently, we show that CIDSTBCs provide coding gain which comes in with negligible increase in the processing complexity at the relays. Subsequently, we design single-symbol ML decodable (SSD) DSTBCs for relay networks with single-antenna nodes. In particular, two classes of SSD DSTBCs referred to as (i) Semi-orthogonal SSD Precoded DSTBCs and (ii) Training-Symbol Embedded (TSE) SSD DSTBCs are proposed. A detailed analysis on the maximal rate of such DSTBCs is presented and explicit DSTBCs achieving the maximal rate are proposed. It is shown that the proposed codes have higher rates than the existing SSD DSTBCs. In the second part, we study two-user Gaussian Multiple Access Channels (GMAC). Capacity regions of two-user GMAC are well known. Though, capacity regions of such channels provide insights into the achievable rate pairs in an information theoretic sense, they fail to provide information on the achievable rate pairs when we consider finitary restrictions on the input alphabets and analyze some real world practical signal constellations like QAM and PSK signal sets. Hence, we study the capacity aspects of two-user GMAC with finite input alphabets. In particular, Constellation Constrained (CC) capacity regions of two-user SISO-GMAC are computed for several orthogonal and non-orthogonal multiple access schemes (abbreviated as O-MA and NO-MA schemes respectively). It is first shown that NO-MA schemes strictly offer larger capacity regions than the O-MA schemes for finite input alphabets. Subsequently, for NO-MA schemes, code pairs based on Trellis Coded Modulation (TCM) are proposed such that any rate pair on the CC capacity region can be approached. Finally, we consider a two-user Multiple-Input Multiple-Output (MIMO) fading MAC and design STBC pairs such that ML decoding complexity is reduced.

One of the most popular ways to exploit the advantages of a multiple-input multiple-output (MIMO) system is using space time block coding. A space time block code (STBC) is a finite set of complex matrices whose entries consist of the information symbols to be transmitted. A linear STBC is one in which the information symbols are linearly combined to form a two-dimensional code matrix. A well known method of maximum-likelihood (ML) decoding of such STBCs is using the sphere decoder (SD). In this thesis, new constructions of STBCs with low sphere decoding complexity are presented and various ways of characterizing and reducing the sphere decoding complexity of an STBC are addressed. The construction of low sphere decoding complexity STBCs is tackled using irreducible matrix representations of Clifford algebras, cyclic division algebras and crossed-product algebras. The complexity reduction algorithms for the STBCs constructed are explored using tree based search algorithms. Considering an STBC as a vector space over the set of weight matrices, the problem of characterizing the sphere decoding complexity is addressed using quadratic form representations. The main results are as follows. A sub-class of fast decodable STBCs known as Block Orthogonal STBCs (BOSTBCs) are explored. A set of sufficient conditions to obtain BOSTBCs are explained. How the block orthogonal structure of these codes can be exploited to reduce the SD complexity of the STBC is then explained using a depth first tree search algorithm. Bounds on the SD complexity reduction and its relationship with the block orthogonal structure are then addressed. A set of constructions to obtain BOSTBCs are presented next using Clifford unitary weight designs (CUWDs), Coordinate-interleaved orthogonal designs (CIODs), cyclic division algebras and crossed product algebras which show that a lot of codes existing in literature exhibit the block orthogonal property. Next, the dependency of the ordering of information symbols on the SD complexity is discussed following which a quadratic form representation known as the Hurwitz-Radon quadratic form (HRQF) of an STBC is presented which is solely dependent on the weight matrices of the STBC and their ordering. It is then shown that the SD complexity is only a function of the weight matrices defining the code and their ordering, and not of the channel realization (even though the equivalent channel when SD is used depends on the channel realization). It is also shown that the SD complexity is completely captured into a single matrix obtained from the HRQF. Also, for a given set of weight matrices, an algorithm to obtain a best ordering of them leading to the least SD complexity is presented using the HRQF matrix.

There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the advent of many new applications over the last few decades. The number of sensor nodes in these applications has also increased tremendously in the order of few hundreds in recent years. A typical sensor node in a WSN consists of circuits like RF transceivers, micro-controllers or DSP, ADCs, sensors, and power supply circuits. The RF transmitter and receiver circuits mainly the frequency synthesizers(synthesis of RF carrier and local oscillator signals in transceivers) consume a significant percentage of its total power due to its high frequency of operation. A charge-pump phase locked loop (CP-PLL) is the most commonly used frequency synthesizer architecture in these applications. The growing demands of WSN applications, such as low power consumption larger number of sensor nodes, single chip solution, and longer duration operation presents several design challenges for these transmitter and frequency synthesizer circuits in these applications and a few are listed below, Low power frequency synthesizer and transmitter designs with better spectral performance is essential for an energy efficient operation of these applications. The spurious tones in the frequency synthesizer output will mix the interference signals from nearby sensor nodes and from other interference sources present nearby ,to degrade the wireless transmitter and receiver performance[1]. With the increased density of sensor nodes (more number of in-band interference sources) and degraded performance of analog circuits in the nano-meter CMOS process technologies, the spur reduction techniques are essential to improve the performance of frequency synthesizers in these applications. A single chip solution of sensor nodes with its analog and digital circuits integrated on the same die is preferred for its low power, low cost, and reduced size implementation. However, the parasitic interactions between these analog and digital sub-systems integrated on a common substrate, degrade the spectral performance of frequency synthesizers in these implementations[2]. Therefore, techniques to improve the mixed signal integration performance of these circuits are in great demand. In this thesis, we present a custom designed energy efficient 2.4 GHz BFSK/ASK transmitter architecture using a low power frequency synthesizer design technique taking advantage of the CMOS technology scaling benefits. Furthermore, a few design guidelinesandsolutionstoimprovethespectralperformanceoffrequency synthesizer circuits and in-turn the performance of transmitters are also presented. The target application being short distance, low power, and battery operated wireless communication applications. The contributions in this thesis are, Spectral performance improvement techniques The CP mismatch current is a dominant source of reference spurs in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect [3]. In this work, we present a CP mismatch current calibration technique using an adaptive body bias tuning of its PMOS transistors. Chip prototype of 2.4 GHzCP-PLLwith the proposed CP calibration technique was fabricated in UMC 0.13 µm CMOS process. Measurements show a CP mismatch current of less than 0.3 µA(0.55 %) using the proposed calibration technique over the VCO control voltage range 0.3 to 1 V. The closed loop PLL measurements using the proposed technique exhibited a 9dB reduction in the reference spur levels across the PLL output frequency range 2.4 -2.5 GHz. The parasitic interactions between analog and digital circuits through the common substrate severely affects the performance of CP-PLLs. In this work, we experimentally demonstrate the effect of periodic switching noise generated from the digital buffers on the performance of charge-pump PLLs. The sensitivity of PLL performance metrics such as output spur level, phase noise, and output jitter are monitored against the variations in the properties of a noise injector digital signal. Measurements from a 500 MHz CP-PLL shows that the pulsed noise injection with the duty cycle of noise injector signal reduced from 50% to 20%, resulted in a 12.53 dB reduction in its output spur level and a 107 ps reduction in its Pk-Pk deterministic period jitter performance. Low power circuit techniques A low power frequency synthesizer design using a digital frequency multiplication technique is presented. The proposed frequency multiply by 3 digital edge combiner design having a very few logic gates, demonstrated a significant reduction in the power consumption of frequency synthesizer circuits, with an acceptable spectral performance suitable for these relaxed performance applications. A few design guidelines and techniques to further improve its spectral performance are also discussed and validated through simulations. Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency multiplier circuits are fabricated in UMC 0.13 µm CMOS process. The 2.4 GHz CP-PLL using the proposed digital frequency multiplication technique (10.7 mW) consumed a much reduced power compared to a conventional implementation(20.3 mW). A custom designed, energy efficient 2.4 GHz BFSK/ASK transmitter architecture using the proposed low power frequency synthesizer design technique is presented. The transmitter uses a class-D power amplifier to drive the 50Ω antenna load. Spur reduction techniques in frequency synthesizers are also used to improve the spectral performance of the transmitter. A chip prototype of the proposed transmitter architecture was implemented in UMC0.13 µm CMOS process. The transmitter consume14 mA current from a 1.3V supply voltage and achieve improved energy efficiencies of 0.91 nJ/bit and 6.1 nJ/bit for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively.

MEMS Sensors are widely used for sensing inertial displacements. The displacements arising out of acceleration /Coriolis effect are typically in the range of 1 nm-1 m. This work investigates the realization of high resolution MEMS inertial sensors using novel displacement sensing mechanisms. Capacitance sensing ASIC is developed as part of conventional electronics interface with MEMS sensor under the conventional CMOS-MEMS integration strategy. The capacitance sense ASIC based on Continuous Time Voltage scheme with coherent and non-coherent demodulation is prototyped on AMS 0.35 m technology. The ASIC was tested to sense C = 3.125 fF over a base of 2 pF using on-chip built-in test capacitors. Dynamic performance of this ASIC was validated by interfacing with a DaCM MEMS accelerometer. 200milli-g of acceleration (equivalent to a C = 2.8 fF) over an input frequency of 20Hz is measurable using the developed ASIC. The observed sensitivity is 90mV/g. The ASIC has several programmable features such as variation in trim capacitance (3.125 fF-12.5 pF), bandwidth selection (500 Hz-20 kHz) and variable gain options (2-100). Capacitance detection, a dominant sensing principle in MEMs sensors, experiences inherent limitation due to the role of parasitics when the displacements of interest are below 5 nm range. The capacitive equivalence ( C) for the range of displacements of the order of 5 nm and below would vary in the range atto-to-zepto farad. Hence there is a need to explore alternative sensing schemes which preferably yield higher sensitivity (than those offered by the conventional integration schemes) and are based on the principle of built-in transduction to help overcome the influence of parasitics on sensitivity. In this regard, 3 non-conventional architectures are explored which fall under the direct integration classification namely: (a) Sub-threshold based sensing (b) Fringe field based sensing and (c) Tunneling current based sensing. a) In Sub-threshold based sensing, FET with a suspended gate is used for displacement sensing. The FET is biased in the sub-threshold region of operation. The exponential modulation of drain current for a change in displacement of 1 nm is evaluated using TCAD, and the in uence of initial air-gap variation on the sensitivity factor ( ID=ID) is brought out. For 1% change in air gap displacement (i.e., TGap/TGap, the gap variation resulting due to the inertial force / mass loading) nearly 1050% change in drain current( ID=ID) is observed (considering initial air gaps of the order 100 nm). This validates the high sensitivity offered by the device in this regime of operation. A comparison of sensitivity estimate using the capacitive equivalence model and TCAD simulated model for different initial air-gaps in a FD-SOI FET is brought out. The influence of FDSOI FET device parameters on sensitivity, namely the variation of TSi, TBox, NA and TGap are explored. CMOS compatibility and fabrication feasibility of this architecture was looked into by resorting to the post processing approach used for validating the sub-threshold bias concept. The IMD layers of the Bulk FETs fabricated through AMS 0.35 technology were etched using BHF and IPA mixture to result in a free standing metal (Al) layers acting as the suspended gate. The performance estimate is carried out considering specific Equivalent Gap Thickness (EGT) of 573 nm and 235 nm, to help overcome the role of coupled electrostatics in influencing the sensitivity metric. The sensitivity observed by biasing this post processed bulk FET in sub-threshold is 114% ( ID=ID change) for a 59% ( d/d change). The equivalent C in this case is 370 aF. b) In Fringe eld based sensing approach, a JunctionLess FET (JLFET) is used as a depletion mode device and an out-of-plane gate displacement would help modulate the device pinch-o voltage due to fringe field coupling. The resulting change in the gate fringe field due to this displacement modulates the drain current of the JunctionLess FET. The displacement induced fringe field change (relative to the FET channel) brings about a distinct shift in the ID-VG characteristics of the JLFET. For displacement d = 2 nm, the JLFET with a channel doping of ND = 8X1018cm 3 and a bias point of VG = -47.7 V, 98% enhancement in sensitivity is observed in 3D TCAD simulations. The equivalent C in this case is 29 zF. The role of ground-planes in the device operation is explored. c) In the tunneling current based sensing approach, the beams fabricated using the SOI-MUMPS process are FIB milled so as to create very ne air gaps of the order of nearly 85 nm. Under high electric fields of the order > 8 MV/cm, the lateral displacement based tunneling sensor offers enhanced change in sensitivity for an induced external force at a fixed DC bias. When integrated as an array with varying electrode overlap, this technique can track displacements over a wide range. With the initial beam overlap as 1.2 m, for a lateral displacement of 1.2 m, a 100% change in sensitivity ( ID=ID) is observed. The effect of fringe field can be completely neglected here unlike its capacitive beam equivalent.

Security of communications is a major requirement for Mobile Adhoc NETworks(MANETs) since they use wireless channel for communications which can be easily tapped, and physical capture of MANET nodes is also quite easy. From the point of view of providing security in MANETs, there are basically two types of MANETs, viz., authoritarian MANETs, in which there exist one or more authorities who decide the members of the network, and self-organized MANETs, in which there is no such authority. Ensuring security of communications in the MANETs is a challenging task due to the resource constraints and infrastructure-less nature of these networks, and the limited physical security of MANET nodes. Attacks on security in a MANET can be launched by either the external attackers which are not legitimate members of the MANET or the internal attackers which are compromised members of the MANET and which can hold some valid security credentials or both. Key management and authentication protocols(KM-APs)play an important role in preventing the external attackers in a MANET. However, in order to prevent the internal attackers, an intrusion detection system(IDS) is essential. The routing protocols running in the network layer of a MANET are most vulnerable to the internal attackers, especially to the attackers which launch packet dropping attack during data packet forwarding in the MANET. For an authoritarian MANET, an arbitrated KM-AP protocol is perfectly suitable, where trusts among network members are coordinated by a trusted authority. Moreover, due to the resource constraints of a MANET, symmetric key management protocols are more efficient than the public key management protocols in authoritarian MANETs. The existing arbitrated symmetric key management protocols in MANETs, that do not use any authentication server inside the network are susceptible to identity impersonation attack during shared key establishments. On the other hand, the existing server coordinated arbitrated symmetric key management protocols in MANETs do not differentiate the role of a membership granting server(MGS) from the role of an authentication server, and so both are kept inside the network. However, keeping the MGS outside the network is more secure than keeping it inside the network for a MANET. Also, the use of a single authentication server inside the network cannot ensure robustness against authentication server compromise. In self-organized MANETs, public key management is more preferable over symmetric key management, since the distribution of public keys does not require a pre-established secure channel. The main problem for the existing self-organized public key management protocols in MANETs is associated with the use of large size certificate chains. Besides, the proactive certificate chaining based approaches require each member of a MANET to maintain an updated view of the trust graph of the entire network, which is highly resource consuming. Maintaining a hierarchy of trust relationships among members of a MANET is also problematic for the same reason. Evaluating the strength of different alternative trust chains and restricting the length of a trust chain used for public key verification is also important for enhancing the security of self-organized public key management protocols. The existing network layer IDS protocols in MANETs that try to defend against packet dropping attack use either a reputation based or an incentive based approach. The reputation based approaches are more effective against malicious principals than the incentive based approaches. The major problem associated with the existing reputation based IDS protocols is that they do not consider the protocol soundness issue in their design objectives. Besides, most of the existing protocols incorporate no mechanism to fight against colluding principals. Also, an IDS protocol in MANETs should incorporate some secure and efficient mechanism to authenticate the control packets used by it. In order to mitigate the above mentioned problems in MANETs, we have proposed new models and designed novel security protocols in this thesis that can enhance the security of communications in MANETs at lesser or comparable cost. First, in order to perform security analysis of KM-AP protocols, we have extended the well known strand space verification model to overcome some of its limitations. Second, we have proposed a model for the study of membership of principals in MANETs with a view to utilize the concept for analyzing the applicability and the performance of KM-AP protocols in different types of MANETs. Third and fourth, we have proposed two novel KM-AP protocols, SEAP and CLPKM, applicable in two different types of MANET scenarios. The SEAP protocol is an arbitrated symmetric key management protocol designed to work in an authoritarian MANET, whereas the CLPKM protocol is a self-organized public key management protocol designed for self-organized MANETs. Fifth, we have designed a novel reputation based network layer IDS protocol, named EVAACK protocol, for the detection of packet dropping misbehavior in MANETs. All of the three proposed protocols try to overcome the limitations of the existing approaches in their respective categories. We have provided rigorous mathematical proofs for the security properties of the proposed protocols. Performance of the proposed protocols have been compared with those of the other existing similar approaches using simulations in the QualNet simulator. In addition, we have also implemented the proposed SEAP and CLPKM protocols on a real MANET test bed to test their performances in real environments. The analytical, simulation and experimentation results confirm the effectiveness of the proposed schemes.

Network coding has emerged as an attractive alternative to routing because of the through put improvement it provides by reducing the number of channel uses. In a wireless scenario, in addition, further improvement can be obtained through Physical layer Network Coding (PNC), a technique in which nodes are allowed to transmit simultaneously, instead of transmitting in orthogonal slots. In this thesis, the design and analysis of network coding schemes are considered, for wireless two-way relaying, multi-user Multiple Access Relay Channel (MARC) and wireline networks. In a wireless two-way relay channel with PNC, the simultaneous transmissions of user nodes result in Multiple Access Interference (MAI) at there lay node. The harmful effect of MAI is the presence of signal set dependent deep channel fade conditions, called singular fade states, under which the minimum distance of the effective constellation at the relay become zero. Adaptively changing the network coding map used at the relay according to channel conditions greatly reduces the impact of this MAI. In this work, we obtain these adaptive PNC maps, which are finite in number ,by completing partially filled Latin Squares and using graph vertex coloring. Having obtained the network coding maps, the set of all possible channel realizations is quantized into a finite number of regions, with a specific network coding map chosen in a particular region and such a quantization is obtained analytically for 2λ-PSK signal set. The performance of the adaptive PNC scheme for two-way relaying is analyzed and tight high SNR upper bounds are obtained for the average end-to-end symbol error probability, in terms of the average error probability of a point-to-point fading channel. The adaptive PNC scheme is generalized for two-way relaying with multiple antennas at the nodes. As an alternative to the adaptive PNC scheme for two-way relaying, a Distributed Space Time Coding (DSTC) scheme is proposed, which effectively re-moves the effect of singular fade states at the transmitting nodes itself without any Channel State Information at the Transmitter (CSIT), and without any need to change the PNC map as a function of channel fade conditions. It is shown that the singular fade states can be viewed equivalently as vector subspaces of C2, which are referred to as the singular fade subspaces. DSTC design criterion to minimize the number of singular fade subspaces and maximize the coding gain is formulated and explicit low decoding complexity DSTC designs are provided. For the K-user MARC, in which K source nodes want to transmit messages to a destination node D with the help of are lay node R, a new PNC scheme is proposed. Use of a many-to-one PNC map with conventional minimum squared Euclidean distance decoding at D, results in a loss of diversity order due to error propagation from the relay node. To counter this, we propose a novel low complexity decoder which offers the maximum diversity order of two. Next, we consider wire line networks and explore the connections between linear network coding, linear index coding and discrete polymatroids, which are the multi-set analogue of matroids. We define a discrete polymatroidal network and show that a fractional vector linear solution over a field Fq exists for a network if and only if the network is discrete polymatroidal with respect to a discrete polymatroid representable over Fq.An algorithm to construct networks starting from certain class of discrete polymatroids is provided. Every representation over Fq for the discrete polymatroid, results in a fractional vector linear solution over Fq for the constructed network. It is shown that a linear solution to an index coding problem exists if and only if there exists a representable discrete polymatroid satisfying certain conditions which are determined by the index coding problem considered. El Rouayheb et. al. showed that the problem of finding a multi-linear representation for a matroid can be reduced to finding a perfect linear index coding solution for an index coding problem obtained from that matroid. Multi-linear representation of a matroid can be viewed as a special case of representation of an appropriate discrete polymatroid. We generalize the result of El Rouayheb et. al. by showing that the problem of finding a representation for a discrete polymatroid can be reduced to finding a perfect linear index coding solution for an index coding problem obtained from that discrete polymatroid.

One of the major applications of wireless sensor networks is to sense accurate and reliable data from the physical environment with or without a priori knowledge of data statistics. To extract accurate data from the physical environment, we investigate spatial data correlation among sensor nodes to develop data accuracy models. We propose three data accuracy models namely Estimated Data Accuracy (EDA) model, Cluster based Data Accuracy (CDA) model and Distributed Cluster based Data Accuracy (DCDA) model with a priori knowledge of data statistics. Due to the deployment of high density of sensor nodes, observed data are highly correlated among sensor nodes which form distributed clusters in space. We describe two clustering algorithms called Deterministic Distributed Clustering (DDC) algorithm and Spatial Data Correlation based Distributed Clustering (SDCDC) algorithm implemented under CDA model and DCDA model respectively. Moreover, due to data correlation in the network, it has redundancy in data collected by sensor nodes. Hence, it is not necessary for all sensor nodes to transmit their highly correlated data to the central node (sink node or cluster head node). Even an optimal set of sensor nodes are capable of measuring accurate data and transmitting the accurate, precise data to the central node. This reduces data redundancy, energy consumption and data transmission cost to increase the lifetime of sensor networks. Finally, we propose a fourth accuracy model called Adaptive Data Accuracy (ADA) model that doesn't require any a priori knowledge of data statistics. ADA model can sense continuous data stream at regular time intervals to estimate accurate data from the environment and select an optimal set of sensor nodes for data transmission to the network. Data transmission can be further reduced for these optimal sensor nodes by transmitting a subset of sensor data using a methodology called Spatio-Temporal Data Prediction (STDP) model under data reduction strategies. Furthermore, we implement data accuracy model when the network is under a threat of malicious attack.