Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (plusieurs Watts) donc peu efficaces énergétiquement. Cette thèse explore différentes approches d’optimisation de l’efficacité énergétique des CAN "flash". Afin de min- imiser la consommation du CAN, il n’y a pas d’Echantillonneur-Bloqueur (EB) en tête du circuit. Les étages d’entrée du codeur sont ainsi exposés à la pleine bande passante du signal, à savoir DC-10GHz. Ceci impose des contraintes très strictes sur la précision temporelle de la détection et de la quantification du signal. L’essentiel de cette thèse est donc concentré sur l’analyse des effets hautes frèquences impactant la conception des éléments frontaux du CAN. La validité et l’efficacité des méthodes présentées sont démontrées par des mesures autour d’un CAN 6 bit 20 GS/s. En em- pruntant les techniques de conception des circuits ultra-rapides et en exploitant le po- tentiel haute-fréquence de la technologie à l’état de l’art SiGe BiCMOS, un circuit complètement analogique a ainsi pu être réalisé. Ce CAN est mono-voie et n’a besoin d’aucune calibration ou correction, ni d’assistance digitale. Avec à peine 1W, ce cir- cuit atteint un record d’efficacité énergétique dans l’état de l’art des CAN rapides non entrelacés. / High speed Analog-to-Digital Converters (ADC) are essential building blocks for the reception and processing in high data rate reception circuits. The flash ADC archi- tecture performs the digitization by comparing the analog input signal to all refer- ence levels of the quantization range simultaneously and is thus the fastest architecture available. In the past the flash architecture has been employed successfully to digitize signals at Nyquist rates beyond 20 GS/s. However the inherent high speed operation has led to power consumptions of several watts and hence to poor energy efficien- cies. This thesis explores approaches to optimize the energy efficiency of flash ADCs. In particular, no dedicated track-and-hold stage is used at the high speed data input. This imposes very stringent requirements on the timing accuracy and level accuracy in the high speed signal distribution to the comparators. The comparators need to ex- hibit a very high speed capability to correctly perform the quantization of the signal against the reference levels. The main focus of this thesis is hence the investigation of design relevant high frequency effects in the analog ADC frontend, such as the bandwidth requirement of overdriven comparators, the data signal distribution over a passive transmission line tree and the dynamic linearity of emitter followers. The correctness and efficacy of the presented methods is demonstrated by measurement results of a 6 bit 20 GS/s Nyquist rate flash ADC fabricated within the context of this work. The demonstrator ADC operates without time interleaving, no calibration or correction whatsoever is needed. By employing design techniques borrowed from high speed analog circuits engineering and by exhausting the high speed potential of a state-of-the-art SiGe BiCMOS production technology, a flash ADC with a record energy efficiency could be realized.

Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non-adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated full-custom mixed-mode and full-digital fast control-pulse generators fabricated in a silicon-on-sapphire (SOS) CMOS commercial foundry process ?? a radio-frequency (RF) CMOS technology. These circuits are, fundamentally, fast monostable multivibrators. Initially, after the design specifications were decided upon, I characterized NFET and PFET devices and a n+-diffusion resistor from 500 nm and 250 nm commercial SOS-CMOS processes. Measuring their conductance curves at 300 300 K, 4.2 2 K, and sub-K (30 30 mK base to 1000 1000 mK) showed that they function with desirable behaviour although exhibiting some deviations from their 300 300 K characteristics. The mixed-mode first generation control-pulse generator was demonstrated showing that it produced dwell-time adjustable pulses with 100 100 ps rise-times at 300 K, 4.2 2 K, and sub-K with a power dissipation of 12 12 uW at 100 100 MHz. The full-digital second generation control-pulse generator was demonstrated showing accurately adjustable dwell-times settable via a control-word streamed synchronously to a shift-register. The design was based on a ripple-counter with provisions for internal or external clocking. This research has demonstrated that SOS-CMOS technology is highly feasible for the fabrication of control microelectronics for a Si:P-based QC. I have demonstrated full-custom SOS-CMOS mixed-mode and full-digital control circuits at 300 300 K, 4.2 2 K, and sub-K which suitable for qubit control.

Cette étude porte sur l'intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d'économies d'énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d'intégration. Cette thèse se propose d'employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l'oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc.

La croissance continue et rapide du trafic de données dans les infrastructures de télécommunications, impose des niveaux de débit de transmission ainsi que de puissance de traitement de l'information, que les capacités intrinsèques des systèmes et microcircuits électroniques ne seront plus en mesure d'assurer à brève échéance : le développement de nouveaux scenarii technologiques s'avère indispensable pour répondre à la demande de bande passante imposée notamment par la révolution de l'internet, tout en préservant une consommation énergétique raisonnable. Dans ce contexte, l'intégration hétérogène fonctionnelle sur silicium de dispositifs photoniques à émission par la surface de type VCSEL utilisant des miroirs large-bandes ultra-compacts à cristaux photoniques constitue une stratégie prometteuse pour surmonter l'impasse technologique actuelle, tout en ouvrant la voie à un développement rapide d'architectures et de systèmes de communications innovants dans le cadre du mariage entre photonique et micro-nano-électronique.

Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non-adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated full-custom mixed-mode and full-digital fast control-pulse generators fabricated in a silicon-on-sapphire (SOS) CMOS commercial foundry process ?? a radio-frequency (RF) CMOS technology. These circuits are, fundamentally, fast monostable multivibrators. Initially, after the design specifications were decided upon, I characterized NFET and PFET devices and a n+-diffusion resistor from 500 nm and 250 nm commercial SOS-CMOS processes. Measuring their conductance curves at 300 300 K, 4.2 2 K, and sub-K (30 30 mK base to 1000 1000 mK) showed that they function with desirable behaviour although exhibiting some deviations from their 300 300 K characteristics. The mixed-mode first generation control-pulse generator was demonstrated showing that it produced dwell-time adjustable pulses with 100 100 ps rise-times at 300 K, 4.2 2 K, and sub-K with a power dissipation of 12 12 uW at 100 100 MHz. The full-digital second generation control-pulse generator was demonstrated showing accurately adjustable dwell-times settable via a control-word streamed synchronously to a shift-register. The design was based on a ripple-counter with provisions for internal or external clocking. This research has demonstrated that SOS-CMOS technology is highly feasible for the fabrication of control microelectronics for a Si:P-based QC. I have demonstrated full-custom SOS-CMOS mixed-mode and full-digital control circuits at 300 300 K, 4.2 2 K, and sub-K which suitable for qubit control.

The development of radio frequency integrated circuits (RFICs), especially the dream of integrating analog, digital and radio frequency (RF) components on the same chip that is commonly known as System-on-a-Chip (SoC), is crucial to mobile communications of the future. Such SoC approach offers enhanced performance, greater reliability, and substantially less power consumption of integrated circuits while reducing overall physical size and thus manufacturing cost. However, the progress has been stalled by the lack of miniaturized inductor elements. Rise of unwanted parasitic effects limits down-scaling of the inductor structures and leaves the use of magnetic coating as a viable and attractive option to enhance the inductance and thus inductance density. It is also essential to shift from perm alloy and other amorphous alloys to ferrites and hex ferrites as the core material because of their very high electrical resistivity so as to keep losses in check, a criterion that cannot be compromised on in GHz frequency applications. This is viable, however, only if the integration of the magnetic core (film), particularly a ferrite film, is fully compatible with the CMOS fabrication process. Various approaches have been taken to meet this requirement, including investigations of employing layers of ferrite materials to envelop the inductor loop. However, the deposition of thin films of ferrites, whether by PVD or CVD, usually calls for the deposited ferrite layer to be annealed at an elevated temperature to crystallize the layer so that its magnetic characteristics are appropriate for the optimum performance of the circuit element. Such annealing is incompatible with CMOS process flow required for aggressive device geometries, as the inductor element is added after the active semiconductor circuit is processed, and any exposure of the processed circuit to elevated temperatures risks disturbing precise doping profiles employed and the integrity of the inter-layer dielectrics. What is called for is a low-temperature process for the deposition of a ferrite layer on top of the patterned inductor element – a layer of thickness such that most of the fringe field is encapsulated – while ensuring that the layer comprises crystallites of uniform size that leads to uniform magnetic behaviour. Recognizing the difficulty of meeting the various stringent requirements, it has recently been remarked that such a goal is a formidable challenge. In an attempt to address this challenge, in this work, we have adopted a counter-intuitive approach - the deposition of the desired ferrite composition on a processed die (that contains the inductor structures along with active semiconductor circuits) by immersing it into a chemical (reactant) solution, followed by a brief irradiation of microwave frequency. However, to identify the desired ferrite composition and the appropriate recipe to deposit them, a systematic effort had to be made first, to understand the inter-relationship between synthesis process, structure of resulting material, and its physical and chemical properties. Therefore, at the beginning, a general introduction in which key concepts related to the magnetic-core inductors, the microwave-irradiation-assisted synthesis of nanostructures, the ‗state of the art‘ in the field of integration of appropriate magnetic material to the RFICs, are all outlined. As a proof of concept, microwave-irradiation-assisted solution-based deposition of zinc ferrite thin films on the technologically important Si (100) substrate is demonstrated. The highlight of the process is the use of only non-toxic metal organic precursors and aqua-alcoholic solvents for the synthesis, which is complete in 10 minutes @< 100 °C, without any poisonous by-products. Effects of various process parameters such as solute concentrations, surfactant types, and their concentrations are investigated. A wide range of deposition rates (10 - 2000 nm/min) has been achieved by tweaking the process parameters. The simultaneous formation of zinc ferrite nanocrystallites (ZFNC) along with deposition of thin film is the hallmark of this synthesis technique. Unlike its bulk counterpart, both film and powder are found upon investigation to be rich in magnetic behavior– owing to plausible cationic distribution in the crystal lattice, induced by the inherently quick and far-from-equilibrium nature of the process. The accurate estimation of magnetic characteristics in film is, however, found to be difficult due to the high substrate-to-film mass ratio. The simultaneously prepared ZFNC is examined to arrive at the optimized process recipe that imparts the desired magnetic properties to the zinc ferrite system. The crystallographic cationic distribution in zinc ferrite powder is, however, difficult to study due to the nanoscale dimension of the as prepared material. To enable crystal growth, slow and rapid annealing in air at two different temperatures are employed. The effects of these annealing schemes on various attributes (magnetic properties in particular) are studied. Rapid annealing turns out to be an interesting pathway to promote rapid grain-growth without disturbing the crystallographic site occupancies. The presence of inversion, i.e., the amount of Fe3+ in the ‗A‘-sites in the spinel structure that ideally is zero in normal spinel structure of zinc ferrite, is evident in all annealed ZFNC, as determined by Riveted analysis. Such partially inverted ZFNC exhibits soft magnetic behavior with high saturation magnetization, which can easily be ―tuned‖ by choosing appropriate annealing conditions. However, a few unique strategic modifications to the same microwave-irradiation-assisted solution-based synthesis technique are tried for the formation of nanocrystalline powder with desired sizes and properties without the necessity of anneal. The approach eventually appears to pave a way for the formation of oriented structures of zinc ferrite. The effects of anneal, nevertheless, are studied with the help of neutron powder diffractometry and magnetic measurements. The magnetic ordering at various temperatures is analyzed and connected to the magnetic measurements. The study shows that long-range magnetic ordering, present even at room temperate, originates from the distribution of cations in the partially inverted spinel structures, induced by the rapid and kinetically driven microwave synthesis. Keeping the mild nature (<200 °C) of the processing in mind, a large degree of inversion (~0.5) is a surprise and results in a very high saturation magnetization, as much as 30 emu/g at room temperature (paramagnetic in bulk), in the ZFNC system. Based on the knowledge of process-structure-property interrelationship, a recipe for the deposition of ferrite thin films by the microwave-assisted deposition technique is optimized. Successful deposition of smooth and uniform zinc ferrite thin films on various substrates is, then, demonstrated. The mystery behind the strong adherence of the film to the substrate - an unexpected outcome of a low-temperature process - is probed by XPS and the formation of silicates at the interface is identified as the probable reason. The uniformity and consistency of film composition is also examined in this chapter. Another salient feature of the process is its capability to coat any complex geometry conformally, allowing the possibility of depositing the material in a way to ―wrap around‖ the three-dimensional inductor structures of RF-CMOS. Integration of nanostructure zinc ferrite thin films onto on-chip spiral inductor structures has been demonstrated successfully. The magnetic-core inductors so obtained exhibit the highest inductance density (700 nH/mm2) and the highest Q factor (~20), reported to date, operate at 5 GHz and above, by far the highest reported to date. An increase in inductance density of as much as 20% was achieved with the use of just 1 µm thick film of zinc ferrite covering only the ―top‖ of the spiral structure, i.e., up to 20% of chip real estate can potentially be freed to provide additional functionality. The microwave-assisted solution-based deposition process described in this thesis is meant for ‗post-CMOS‘ processing, wherein the film deposited on some specific electronic components can add desired functionality to or improve the performance of a component (circuit) underneath. However, the effect of such ‗post-CMOS‘ processing on the active MOS devices, interconnects, and even inter-layer-dielectrics fabricated prior to the deposition has to be mild enough to leave the performance of delicate MOS characteristics intact. Such CMOS-compatibility of the present deposition process has been tested with a satisfactorily positive result.

Les capteurs d'images en technologie CMOS se sont fortement développés grâce à l'avènement du multimédia à la fin des années 1990. Leurs caractéristiques optiques, ainsi que leur coût, les ont, en effet, destinés au marché “grand public”. Ces capteurs intègrent des fonctions analogiques et/ou numériques qui permettent la mise en œuvre de traitements au sein du pixel, autour du pixel, pour un groupe de pixels, en bout de colonne. Jusqu’à présent, les traitements intégrés dans le capteur sont de nature linéaire et consistent en général à réaliser des convolutions. Si ces traitements sont incontournables dans une chaîne de vision, ils sont toutefois limités et ne permettent pas à eux seuls de réaliser une application complexe du type reconnaissance d’objets dans une scène naturelle. Pour cela, des traitements non-linéaires associés à des classifieurs haut-niveau permettent de compléter les traitements linéaires en vue de répondre aux contraintes d’une application complexe. Dans ce contexte, nous montrons que les approches “mathématique-inspirées” et “neuro-inspirées” nécessitent toutes deux l'emploi de traitements non-linéaires basés sur les opérateurs "min" et "max". De ce fait, nous proposons un modèle architectural permettant d'intégrer dans le plan focal les traitements non-linéaires. Ce modèle est basé sur une topologie de PEs 4-connexes et présente un double avantage par rapport aux solutions classiques. D'une part pour ce qui concerne l'augmentation de la vitesse d'exécution des traitements non linéaires mais aussi pour les aspects de réduction de la consommation qui sont liés aux nombres d'accès aux mémoires externes dans le cas des systèmes numériques. Le circuit NLIP (Non Linear Image processing) qui a été conçu durant cette thèse comporte 64 x 64 pixels associés à 64 x 64 processeurs analogiques élémentaires. Chaque pixel a une taille de 40 m de côté et présente un facteur de remplissage de 18% ce qui garantit une bonne sensibilité. La fabrication du circuit a été réalisée en technologie CMOS 0.35 m et les tests fonctionnels réalisés ont permis de valider le modèle de rétine proposé / CMOS images sensors have grown significantly since the late 1990s in connection with the huge developments of multimedia applications. Their optical characteristics, as well as their cost, have, in fact targeted for the consumer market. These sensors include analog and / or digital functions that allow the implementation of treatments within the pixel around the pixel, for a group of pixels in the end of column. Until now, processing inside the sensor.Until now, image processing inside the CMOS sensor are linear and based on convolutions. If these treatments are essential in a chain of vision, they are however limited and do not allow themselves to make a complex application like objects recognition in a natural scene. For this, non-linear associated with high-level classifiers can complete linear processing to meet the demands of a complex application. In this context, we show that “mathematically inspired” and “neuron-inspired” approaches both require the use of non-linear operators based on the “min” and “max” treatments. Therefore, we propose an architectural model for integrating non-linear processes in the focal plane. This model is based on a topology of “4-connected” PE and has two advantages over conventional solutions. Firstly with regard to increasing the speed of execution of nonlinear treatments but also aspects of reduced consumption are related to access to external memory in the case of digital based systems. The NLIP circuit (Non Linear Image Processing), which was designed during this thesis has 64 x 64 pixels associated with 64 x 64 elementary analog processors. Each pixel has a size of 40 m from the side and has a fill factor of 18%, which ensures a good sensitivity. The fabrication of the circuit was carried out in CMOS technology 0.35 m and functional tests were used to validate the proposed model retina

The temperature sensor design discussed in this thesis, is meant mainly to monitor temperature at power outlets. Current variations in power cords have a direct impact on the surrounding temperature. Sensing these variations ,enables us to take necessary measures to prevent any hazards due to temperature rise. Thus, for this application we require a sensor with a moderate temperature error (_10C) over a sensing range of -200C to 1500C. Low power consumption and simple digitizing scheme alleviate measurement errors due to self heating effects of the sensor. A current starved inverter based ring oscillator was chosen for the sensor design in 130nm technology. The inverter delay variation with temperature is used for sensing. Linearity and process invariancy of these characteristics are fundamental to the sensor design. We observed through simulations, and confirmed by mathematical analysis, that the sensing characteristics are governed by bias current dependence on temperature. Control voltage for the bias circuitry of the oscillator determines current through the inverter stages. Hence, for linear sensing characteristics, a control voltage(Vc) just above the maximum threshold voltage of bias transistor is used. This enables generation of PTAT saturation current for current starved inverters, due to dominance of threshold voltage decrease with temperature over mobility decrease. I.Another limitation, process dependency of the sensing characteristics, was overcome through the proposed calibration based compensation technique. A changing Vc proportional to threshold voltage variation with process, process independent bias current and current temperature characteristics were obtained. This compensated for the process variation effects on frequency. Thus, a variable Vc was generated using a reference with low temperature sensitivity of 17.6_V=0C, and resistive divider combinations for various processes. Incorporating this compensation technique we achieved good linearity in sensor characteristics and a maximum temperature error of± 1.60C over the sensing range. The sensor consumes a low power of 0.29mW and also occupies minimal area.

En exploitant la fonction d’amplification intrinsèque fournie par les transistors UTBB FDSOI, nous avons présenté des ISFET ultra sensibles. L'intégration de la fonctionnalité de détection a été réalisée en back end of line (BEOL), ce qui offre les avantages d'une fiabilité et d'une durée de vie accrues du capteur, d'une compatibilité avec le processus CMOS standard et d'une possibilité d'intégration d'un circuit diviseur capacitif. Le fonctionnement des MOSFETs, sans une polarisation appropriée de la grille avant, les rend vulnérables aux effets de grilles flottantes indésirables. Le circuit diviseur capacitif résout ce problème en polarisant la grille avant tout en maintenant la fonctionnalité de détection sur la même grille par un couplage capacitif au métal commun du BEOL. Par conséquent, le potentiel au niveau du métal BEOL est une somme pondérée du potentiel de surface au niveau de la grille de détection et de la polarisation appliquée au niveau de la grille de contrôle. Le capteur proposé est modélisé et simulé à l'aide de TCAD-Sentaurus. Un modèle mathématique complet a été développé. Il fournit la réponse du capteur en fonction du pH de la solution (entrée du capteur) et des paramètres de conception du circuit diviseur capacitif et du transistor UTBB FDSOI. Dans ce cas, des résultats cohérents ont été obtenus des travaux de modélisation et de simulation, avec une sensibilité attendue de 780 mV / pH correspondant à un film de détection ayant une réponse de Nernst. La modélisation et la simulation du capteur proposé ont également été validées par une fabrication et une caractérisation du capteur de pH à grille étendue avec validation de son concept. Ces capteurs ont été développés par un traitement séparé du composant de détection de pH, qui est connecté électriquement au transistor uniquement lors de la caractérisation du capteur. Ceci permet une réalisation plus rapide et plus simple du capteur sans avoir besoin de masques et de motifs par lithographie. Les capteurs à grille étendue ont présenté une sensibilité de 475 mV/pH, ce qui est supérieur aux ISFET de faible puissance de l'état de l’art. Enfin, l’intégration de la fonctionnalité de détection directement dans le BEOL des dispositifs FDSOI UTBB a été poursuivie. Une sensibilité expérimentale de 730 mV/pH a été obtenue, ce qui confirme le modèle mathématique et la réponse simulée. Cette valeur est 12 fois supérieure à la limite de Nernst et supérieure aux capteurs de l'état de l’art. Les capteurs sont également évalués pour la stabilité, la résolution, l'hystérésis et la dérive dans lesquels d'excellentes performances sont démontrées. / Exploiting the intrinsic amplification feature provided by UTBB FDSOI transistors, we demonstrated ultrahigh sensitive ISFETs. Integration of the sensing functionality was made in the BEOL which gives the benefits of increased reliability and life time of the sensor, compatibility with the standard CMOS process, and possibility for embedding a capacitive divider circuit. Operation of the MOSFETs without a proper front gate bias makes them vulnerable for undesired floating body effects. The capacitive divider circuit addresses these issues by biasing the front gate simultaneously with the sensing functionality at the same gate through capacitive coupling to a common BEOL metal. Therefore, the potential at the BEOL metal would be a weighted sum of the surface potential at the sensing gate and the applied bias at the control gate. The proposed sensor is modeled and simulated using TCAD-Sentaurus. A complete mathematical model is developed which provides the output of the sensor as a function of the solution pH (input to the sensor), and the design parameters of the capacitive divider circuit and the UTBB FDSOI transistor. In that case, consistent results have been obtained from the modeling and simulation works, with an expected sensitivity of 780 mV/pH corresponding to a sensing film having Nernst response. The modeling and simulation of the proposed sensor was further validated by a proof of concept extended gate pH sensor fabrication and characterization. These sensors were developed by a separated processing of just the pH sensing component, which is electrically connected to the transistor only during characterization of the sensor. This provides faster and simpler realization of the sensor without the need for masks and patterning by lithography. The extended gate sensors showed 475 mV/pH sensitivity which is superior to state of the art low power ISFETs. Finally, integration of the sensing functionality directly in the BEOL of the UTBB FDSOI devices was pursued. An experimental sensitivity of 730 mV/pH is obtained which is consistent with the mathematical model and the simulated response. This is more than 12-times higher than the Nernst limit, and superior to state of the art sensors. Sensors are also evaluated for stability, resolution, hysteresis, and drift in which excellent performances are demonstrated.

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