Designing new microprocessors is a time consuming task. Architects rely on slow simulators to evaluate performance and a significant proportion of the design space has to be explored before an implementation is chosen. This process becomes more time consuming when compiler optimisations are also considered. Once the architecture is selected, a new compiler must be developed and tuned. What is needed are techniques that can speedup this whole process and develop a new optimising compiler automatically. This thesis proposes the use of machine-learning techniques to address architecture/compiler co-design. First, two performance models are developed and are used to efficiently search the design space of amicroarchitecture. These models accurately predict performance metrics such as cycles or energy, or a tradeoff of the two. The first model uses just 32 simulations to model the entire design space of new applications, an order of magnitude fewer than state-of-the-art techniques. The second model addresses offline training costs and predicts the average behaviour of a complete benchmark suite. Compared to state-of-the-art, it needs five times fewer training simulations when applied to the SPEC CPU 2000 and MiBench benchmark suites. Next, the impact of compiler optimisations on the design process is considered. This has the potential to change the shape of the design space and improve performance significantly. A new model is proposed that predicts the performance obtainable by an optimising compiler for any design point, without having to build the compiler. Compared to the state-of-the-art, this model achieves a significantly lower error rate. Finally, a new machine-learning optimising compiler is presented that predicts the best compiler optimisation setting for any new program on any new microarchitecture. It achieves an average speedup of 1.14x over the default best gcc optimisation level. This represents 61% of the maximum speedup available, using just one profile run of the application.

Modern network technologies were not designed for high assurance applications. As the DOD moves towards implementing the Global Information Grid (GIG), hardened networks architectures will be required. The Monterey Security Architecture (MYSEA) is one such project. This work addresses the issue of object reuse as it pertains to volatile memory spaces in untrusted MYSEA clients. When a MYSEA client changes confidentiality levels, it is possible that classified material remains in volatile system memory. If the system is not power cycled before the next the login, an attacker could retrieve sensitive information from the previous session. This thesis presents a conceptual design to protect against such an attack. A processor may undergo a hard or soft reboot. The proposed design uses a secure coprocessor to sense the reboot type of the host platform. In addition, a count is kept of the number of hard reboots the host platform has undergone. Using services provided by the secure coprocessor, the host platform can trustfully attest to a remote entity that it has undergone a hard reboot. This addresses the MYSEA object reuse problem. The design was tested using the CPU simulator software SimpleScalar.

The warfighter constantly needs increased accuracy from GPS and a means to increasing this accuracy to the decimeter level is a broadcast ephemeris message containing GPS satellite orbit and clock corrections. The ephemeris message is produced at the GPS MCS (Master Control Station) which receives GPS signal data from NGA and Air Force worldwide and uses sophisticated software to produce the orbit and clock corrections. The problem is getting the ephemeris message to the tactical user in a forward operating area. This thesis proposed a notional architecture for pushing the ephemeris message to the tactical user. It then modeled the architecture and simulated the broadcast of the ephemeris message to a tactical user using NETWARS. The baseline architecture was simulated and analyzed and then additional constraints were placed upon the network to simulate a real-world model. The simulation results demonstrated that the architecture was feasible for ephemeris message broadcast with the constraints on time intervals between broadcasts, residual traffic and message size.

The United States is in the midst of an ambitious effort to build and deploy a wide range of ballistic missile defense systems. These ballistic missile defense systems will be effective against a host of current and postulated threats from ballistic missiles. In this thesis study, we explore the process of enhancing the effectiveness of weapon assignment for a system of systems. First, analysis of information is drawn from current proposed system of the ABM and its construction from the ground up. This research analyzes two ballistic Missile Defense System (BMDS), Aegis and Patriot respectively, their attributes, and their current and future roles in a Global Ballistic Defense Missile System. In addition, this thesis presents a software architecture for the ABM weapon assignment component module with object oriented design feasibility with integration as the key ingredient. This research contributed to highlighting some shortfalls in efforts to integrate capabilities and desired capabilities as the missile threat evolves and presents recommendations for follow-on research to improve ABM's weapon assignment capabilities.

Extensible Markup Language (XML) has had a revolutionary effect on information technology. Both business and government have adopted XML as the format of choice for information sharing. Business uses XML to leverage the full potential of the Internet for e-Commerce. The government wants to leverage the ability to share information across many platforms between divergent agencies. In particular, in August 2004, Executive Order (EO) 13356 called for improved sharing of terrorist information to protect Americans.[1] XML provides a way to format information so that it is interoperable. The economic benefit of sharing data and resources is apparent. Sharing information between government agencies will assist in national security. However, there is still a requirement to control the flow and state of data. Therefore, access controls must be used to ensure data and information are protected. This thesis asks whether it is possible to provide a survey and analysis of how industry is enforcing access control on XML data, information, and documents that could serve as a foundation for XML security architectures for the government.

Approved for public release; distribution is unlimited / The goal of much work in Virtual Environments (VEs) to date has been to produce innovative technology but until recently, there has been very little user-centered, usability-focused research in VEs that will turn interesting applications into usable ones. There is beginning to be at least some awareness of the need for usability engineering within the VE community. A handful of articles address usability concerns for particular parts of the VE usability space. From this point Gabbard and Hix [1997] has proposed a taxonomy about usability characteristics in VEs to help VE usability engineers and designers. This taxonomy can be used to learn characteristics of VEs or to develop usability engineering methodologies specifically for VEs. In this study, we built hypermedia representation of the taxonomy and evaluated the effectiveness of the user interface by using scenario based formative usability engineering method that developed by Hix and Hartson [1993]. First, we discussed the need for usability engineering for VEs and took a look at a proposed usability engineering methodology [Gabbard and others, 1999] for VEs. Second we implemented hypermedia based web-site taxonomy and then evaluated it iteratively. Last, we added a new study to show the dynamic nature of web-site application. / Lieutenant Junior Grade, Turkish Navy

The breakdown of Dennard's transistor scaling has driven computing systems toward application-specific accelerators, which can provide orders-of-magnitude improvements in performance and energy efficiency over general-purpose processors. To enable the radical departures from conventional approaches that heterogeneous systems entail, research infrastructure must be able to model processors, memory and accelerators, as well as system-level changes---such as operating system or instruction set architecture (ISA) innovations---that might be needed to realize the accelerators' potential. Unfortunately, existing simulation tools that can support such system-level research are limited by the lack of fast, scalable machine emulators to drive execution. To fill this need, in this dissertation we first present a novel machine emulator design based on dynamic binary translation that makes the following improvements over the state of the art: it scales on multicore hosts while remaining memory efficient, correctly handles cross-ISA differences in atomic instruction semantics, leverages the host floating point (FP) unit to speed up FP emulation without sacrificing correctness, and can be efficiently instrumented to---among other possible uses---drive the execution of a full-system, cross-ISA simulator with support for accelerators. We then demonstrate the utility of machine emulation for studying heterogeneous systems by leveraging it to make two additional contributions. First, we quantify the trade-offs in different coupling models for on-chip accelerators. Second, we present a technique to reuse the private memories of on-chip accelerators when they are otherwise inactive to expand the system's last-level cache, thereby reducing the opportunity cost of the accelerators' integration.

K.Y. Mok. / Thesis (M.Ph.)--Chinese University of Hong Kong, 1986. / Bibliography: leaf 96.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaves 119-122. / by Thomas Lee Anderson. / M.S.

Liu, Zhouyi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 110-114). / Abstracts in English and Chinese. / ABSTRACTS --- p.I / 摘要 --- p.II / CONTENTS --- p.III / LIST OF FIGURE --- p.V / LIST OF TABLE --- p.VI / ACKNOWLEDGEMENT --- p.VII / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- NETWORK-ON-CHIP --- p.1 / Chapter 1.2 --- RELATED WORKS --- p.2 / Chapter 1.3 --- PLATFORM OVERVEW --- p.6 / Chapter 1.4 --- AUTHOR'S CONTRIBUTION --- p.10 / Chapter CHAPTER 2 --- NOC LIBRARY --- p.12 / Chapter 2.1 --- NETWORK TERMINOLOGY --- p.12 / Chapter 2.2 --- BASIC STRUCTURE --- p.15 / Chapter 2.3 --- LOW-POWER ORIENTED ARCHITECTURE --- p.20 / Chapter 2.3.1 --- Low-Cost Allocator Design --- p.21 / Chapter 2.3.2 --- Clock Gating --- p.22 / Chapter 2.3.3 --- Express Virtual Channel Insertion --- p.22 / Chapter 2.4 --- LOW-LATENCY ORIENTED ARCHITECTURE --- p.28 / Chapter 2.4.1. --- Lookahead Bypass Scheme --- p.29 / Chapter 2.4.2. --- Lookahead Bypass Router Architecture --- p.29 / Chapter CHAPTER 3 --- BENCHMARK AND MEASUREMENT --- p.31 / Chapter 3.1 --- BENCHMARK GENERATION --- p.32 / Chapter 3.1.1 --- Types of Traffic Patterns --- p.32 / Chapter 3.1.2 --- Traffic Generator --- p.36 / Chapter 3.2 --- MEASUREMENT SETTING --- p.38 / Chapter 3.2.1 --- Warming-up Period. --- p.38 / Chapter 3.2.2 --- Latency Definition --- p.39 / Chapter 3.2.3 --- Throughput Definition --- p.40 / Chapter 3.2.4 --- Virtual Channel Utilization --- p.40 / Chapter CHAPTER 4 --- PLATFORM STRUCTURE --- p.41 / Chapter 4.1 --- FILE TREE --- p.42 / Chapter 4.1.1 --- System Files --- p.46 / Chapter 4.1.2 --- Low-Power NoC Related --- p.47 / Chapter 4.1.3 --- Low-Latency NoC Related --- p.50 / Chapter 4.1.4 --- Project Related --- p.51 / Chapter 4.2 --- PROCESSES --- p.52 / Chapter 4.3 --- GUI ACCESS --- p.56 / Chapter 4.3.1 --- Section 1: Project Setup --- p.58 / Chapter 4.3.2 --- Section 2-a: Low-Power Router Structure --- p.59 / Chapter 4.3.3 --- Section 2-b: Low-Latency Router Structure --- p.60 / Chapter 4.3.4 --- Section 3: Benchmark & Measurement --- p.60 / Chapter 4.3.5 --- Section 4: View Result --- p.62 / Chapter 4.3.6 --- Low-Power NoC Example --- p.62 / Chapter CHAPTER 5 --- OPTIMIZATION AND COMPARISON --- p.72 / Chapter 5.1 --- OPTIMIZATION TECHNIQUE --- p.72 / Chapter 5.1.1 --- Optimization Phase 1: Inactive Buffer Removal --- p.73 / Chapter 5.1.2 --- Optimization Phase 2: Infighting Analysis --- p.74 / Chapter 5.1.3 --- Over-Optimization --- p.75 / Chapter 5.1.4 --- Optimization Example --- p.79 / Chapter 5.2 --- NOCS COMPARISON --- p.83 / Chapter 5.3 --- LOW-POWER IMPLEMENTATION CODE EXPORT --- p.88 / Chapter CHAPTER 6 --- SUMMARY AND FUTURE WORK --- p.92 / Chapter 6.1. --- SUMMARY --- p.92 / Chapter 6.2. --- FUTURE WORK --- p.93 / REFERENCES --- p.95