Power devices play key roles in the power electronics applications. In order for the power electronics designers to fully utilize the performance advantages of power devices, compact power device models are needed in the circuit simulator (Saber, P-spice, etc.). Therefore, it is very important to get accurate device models. However, there are many challenges due to the development of new power devices with new internal structure and new semiconductor materials (SiC, GaN, etc.). In this dissertation, enhanced power diode model is presented with an improvement in the reverse blocking region. In the current power diode model in the Saber circuit simulator, an empirical approach was used to describe the low-bias reverse blocking region by introducing an effect called "conduction loss," a parameter that causes a linear relationship between the device voltage and current at low bias voltages with no physics meaning. Furthermore, this term is not sufficient to accurately describe the changes to the device characteristics as the junction temperature is varied. In the enhanced model, an analytical temperature dependent model for the reverse blocking characteristics has been developed for Schottky/JBS diodes by including the thermionic-emission mechanism in the low-bias range. The newly derived model equations have been implemented in Saber circuit simulator using MAST language. An automated parameter extraction software package developed for constructing silicon (Si) and silicon carbide (SiC) power diode models, which is called DIode Model Parameter extrACtion Tools (DIMPACT). This software tool extracts the data necessary to establish a library of power diode component models and provides a method for quantitatively comparing between different types of devices and establishing performance metrics for device development. This dissertation also presents a new Saber-compatible approach for modeling the inter-electrode capacitances of the Si CoolMOSTM transistor. This new approach accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. The comparison between the simulated data with the measured results validates the accuracy of the new physical model. / Ph. D.

The ultimate goal for power electronics is to convert one form of raw electrical energy into a usable power source with the lowest amount of loss. A considerable portion of these losses are due to the use of switching devices themselves. Device losses can be apportioned to conduction loss and switching loss. It is commonly known and practiced that conduction loss can be reduced by driving MOSFETs and IGBTs harder with gate voltages closer to the maximum rating. This lowers the voltage across the device in the path of the amplified current and ultimately reduces power dissipated by the device. However, switching losses of these devices are not as easily characterized or intuitive for power electronics designers. This is mainly due to the fact that the parasitic reactive elements are nonlinear and not as readily documented as I-V characteristics of a given power device. For example, non-linear parasitic capacitances in the device are given for a fixed frequency across a voltage sweep. Parasitic inductance is typically not even mentioned in the datasheet. The switching losses of these devices depend on these mysterious reactances. A functional way to obtain estimates of switching loss is to test the device under the conditions the device will be used. However, this task must be approached carefully in order to accurately measure the voltage and current of the device. Measurement devices also have parasitic impedances of their own that can add or subtract to switching energy during turn on or turn off and create misleading results. Preliminary testing was performed on multiple devices. After preliminary testing and deliberation, a device-measurement printed circuit board was made to easily replace switching devices of the same package. This thesis presents switching loss measurements of medium-power capable devices in the tens of kW range. It also aims to attribute characteristics of switching voltage and current waveforms to the internal structure of the devices. The device tester designed is versatile since the output buffer of the gate drive is comprised of D-PAK totem pole BJTs. This is able to drive both current and voltage driven devices, i.e. SiC J-FETs (current-driven) and other voltage-driven devices (i.e. MOSFETs and IGBTs). It also allows for TO-220 and TO-247 packaged power diodes. / Master of Science